156 lines
4.4 KiB
C
156 lines
4.4 KiB
C
/*
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* Coherency fabric (Aurora) support for Armada 370 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory Clement <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada 370 and Armada XP SOCs have a coherency fabric which is
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* responsible for ensuring hardware coherency between all CPUs and between
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* CPUs and I/O masters. This file initializes the coherency fabric and
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* supplies basic routines for configuring and controlling hardware coherency
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <asm/smp_plat.h>
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#include "armada-370-xp.h"
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/*
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* Some functions in this file are called very early during SMP
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* initialization. At that time the device tree framework is not yet
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* ready, and it is not possible to get the register address to
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* ioremap it. That's why the pointer below is given with an initial
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* value matching its virtual mapping
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*/
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static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
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static void __iomem *coherency_cpu_base;
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/* Coherency fabric registers */
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#define COHERENCY_FABRIC_CFG_OFFSET 0x4
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#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
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static struct of_device_id of_coherency_table[] = {
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{.compatible = "marvell,coherency-fabric"},
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{ /* end of list */ },
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};
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#ifdef CONFIG_SMP
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int coherency_get_cpu_count(void)
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{
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int reg, cnt;
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reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
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cnt = (reg & 0xF) + 1;
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return cnt;
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}
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#endif
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/* Function defined in coherency_ll.S */
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int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
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int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
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{
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if (!coherency_base) {
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pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
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pr_warn("Coherency fabric is not initialized\n");
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return 1;
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}
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return ll_set_cpu_coherent(coherency_base, hw_cpu_id);
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}
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static inline void mvebu_hwcc_sync_io_barrier(void)
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{
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writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
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while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
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}
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static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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if (dir != DMA_TO_DEVICE)
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mvebu_hwcc_sync_io_barrier();
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return pfn_to_dma(dev, page_to_pfn(page)) + offset;
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}
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static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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if (dir != DMA_TO_DEVICE)
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mvebu_hwcc_sync_io_barrier();
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}
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static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir)
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{
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if (dir != DMA_TO_DEVICE)
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mvebu_hwcc_sync_io_barrier();
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}
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static struct dma_map_ops mvebu_hwcc_dma_ops = {
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.alloc = arm_dma_alloc,
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.free = arm_dma_free,
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.mmap = arm_dma_mmap,
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.map_page = mvebu_hwcc_dma_map_page,
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.unmap_page = mvebu_hwcc_dma_unmap_page,
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.get_sgtable = arm_dma_get_sgtable,
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.map_sg = arm_dma_map_sg,
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.unmap_sg = arm_dma_unmap_sg,
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.sync_single_for_cpu = mvebu_hwcc_dma_sync,
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.sync_single_for_device = mvebu_hwcc_dma_sync,
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.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
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.sync_sg_for_device = arm_dma_sync_sg_for_device,
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.set_dma_mask = arm_dma_set_mask,
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};
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static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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{
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struct device *dev = __dev;
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if (event != BUS_NOTIFY_ADD_DEVICE)
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return NOTIFY_DONE;
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set_dma_ops(dev, &mvebu_hwcc_dma_ops);
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return NOTIFY_OK;
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}
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static struct notifier_block mvebu_hwcc_platform_nb = {
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.notifier_call = mvebu_hwcc_platform_notifier,
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};
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int __init coherency_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, of_coherency_table);
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if (np) {
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pr_info("Initializing Coherency fabric\n");
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coherency_base = of_iomap(np, 0);
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coherency_cpu_base = of_iomap(np, 1);
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set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
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bus_register_notifier(&platform_bus_type,
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&mvebu_hwcc_platform_nb);
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}
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return 0;
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}
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