248 lines
6.8 KiB
C
248 lines
6.8 KiB
C
/*
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* linux/arch/arm/mach-omap1/time.c
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*
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* OMAP Timers
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*
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* Copyright (C) 2004 Nokia Corporation
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* Partial timer rewrite and additional dynamic tick timer support by
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* Tony Lindgen <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* MPU timer code based on the older MPU timer code for OMAP
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/sched_clock.h>
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#include <mach/hardware.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include "iomap.h"
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#include "common.h"
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#ifdef CONFIG_OMAP_MPU_TIMER
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#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
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#define OMAP_MPU_TIMER_OFFSET 0x100
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typedef struct {
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u32 cntl; /* CNTL_TIMER, R/W */
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u32 load_tim; /* LOAD_TIM, W */
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u32 read_tim; /* READ_TIM, R */
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} omap_mpu_timer_regs_t;
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#define omap_mpu_timer_base(n) \
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((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
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(n)*OMAP_MPU_TIMER_OFFSET))
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static inline unsigned long notrace omap_mpu_timer_read(int nr)
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{
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omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
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return readl(&timer->read_tim);
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}
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static inline void omap_mpu_set_autoreset(int nr)
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{
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omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
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writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
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}
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static inline void omap_mpu_remove_autoreset(int nr)
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{
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omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
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writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
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}
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static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
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int autoreset)
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{
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omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
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unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
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if (autoreset)
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timerflags |= MPU_TIMER_AR;
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writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
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udelay(1);
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writel(load_val, &timer->load_tim);
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udelay(1);
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writel(timerflags, &timer->cntl);
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}
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static inline void omap_mpu_timer_stop(int nr)
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{
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omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
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writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
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}
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/*
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* ---------------------------------------------------------------------------
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* MPU timer 1 ... count down to zero, interrupt, reload
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* ---------------------------------------------------------------------------
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*/
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static int omap_mpu_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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omap_mpu_timer_start(0, cycles, 0);
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return 0;
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}
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static void omap_mpu_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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omap_mpu_set_autoreset(0);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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omap_mpu_timer_stop(0);
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omap_mpu_remove_autoreset(0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device clockevent_mpu_timer1 = {
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.name = "mpu_timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = omap_mpu_set_next_event,
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.set_mode = omap_mpu_set_mode,
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};
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static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_mpu_timer1;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction omap_mpu_timer1_irq = {
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.name = "mpu_timer1",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = omap_mpu_timer1_interrupt,
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};
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static __init void omap_init_mpu_timer(unsigned long rate)
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{
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setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
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omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
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clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
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clockevent_mpu_timer1.shift);
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clockevent_mpu_timer1.max_delta_ns =
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clockevent_delta2ns(-1, &clockevent_mpu_timer1);
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clockevent_mpu_timer1.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_mpu_timer1);
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clockevent_mpu_timer1.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_mpu_timer1);
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}
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/*
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* ---------------------------------------------------------------------------
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* MPU timer 2 ... free running 32-bit clock source and scheduler clock
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* ---------------------------------------------------------------------------
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*/
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static u32 notrace omap_mpu_read_sched_clock(void)
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{
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return ~omap_mpu_timer_read(1);
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}
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static void __init omap_init_clocksource(unsigned long rate)
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{
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omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
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static char err[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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omap_mpu_timer_start(1, ~0, 1);
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setup_sched_clock(omap_mpu_read_sched_clock, 32, rate);
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if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
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300, 32, clocksource_mmio_readl_down))
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printk(err, "mpu_timer2");
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}
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static void __init omap_mpu_timer_init(void)
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{
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struct clk *ck_ref = clk_get(NULL, "ck_ref");
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unsigned long rate;
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BUG_ON(IS_ERR(ck_ref));
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rate = clk_get_rate(ck_ref);
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clk_put(ck_ref);
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/* PTV = 0 */
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rate /= 2;
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omap_init_mpu_timer(rate);
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omap_init_clocksource(rate);
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}
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#else
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static inline void omap_mpu_timer_init(void)
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{
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pr_err("Bogus timer, should not happen\n");
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}
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#endif /* CONFIG_OMAP_MPU_TIMER */
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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* ---------------------------------------------------------------------------
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*/
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static void __init omap1_timer_init(void)
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{
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if (omap_32k_timer_init() != 0)
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omap_mpu_timer_init();
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}
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struct sys_timer omap1_timer = {
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.init = omap1_timer_init,
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};
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