Keith Busch b69e2ef24b nvme-pci: dma read memory barrier for completions ... Control dependencies do not guarantee load order across the condition, allowing a CPU to predict and speculate memory reads. Commit 324b494c28 inlined verifying a new completion with its handling. At least one architecture was observed to access the contents out of order, resulting in the driver using stale data for the completion. Add a dma read barrier before reading the completion queue entry and after the condition its contents depend on to ensure the read order is determinsitic. Reported-by: John Garry <john.garry@huawei.com> Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Keith Busch <kbusch@kernel.org> Tested-by: John Garry <john.garry@huawei.com> Acked-by: Will Deacon <will@kernel.org> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Christoph Hellwig <hch@lst.de>		2020-05-12 18:02:24 +02:00
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host	nvme-pci: dma read memory barrier for completions	2020-05-12 18:02:24 +02:00
target	block-5.7-2020-04-10	2020-04-10 10:06:54 -07:00
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Makefile	…