172 lines
4.4 KiB
C
172 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* PTP hardware clock driver for the IDT 82P33XXX family of clocks.
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*
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* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#ifndef PTP_IDT82P33_H
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#define PTP_IDT82P33_H
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#include <linux/ktime.h>
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#include <linux/workqueue.h>
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/* Register Map - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf */
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#define PAGE_NUM (8)
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#define _ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
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#define _PAGE(addr) (((addr) >> 0x7) & 0x7)
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#define _OFFSET(addr) ((addr) & 0x7f)
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#define DPLL1_TOD_CNFG 0x134
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#define DPLL2_TOD_CNFG 0x1B4
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#define DPLL1_TOD_STS 0x10B
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#define DPLL2_TOD_STS 0x18B
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#define DPLL1_TOD_TRIGGER 0x115
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#define DPLL2_TOD_TRIGGER 0x195
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#define DPLL1_OPERATING_MODE_CNFG 0x120
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#define DPLL2_OPERATING_MODE_CNFG 0x1A0
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#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
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#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
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#define DPLL1_PHASE_OFFSET_CNFG 0x143
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#define DPLL2_PHASE_OFFSET_CNFG 0x1C3
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#define DPLL1_SYNC_EDGE_CNFG 0X140
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#define DPLL2_SYNC_EDGE_CNFG 0X1C0
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#define DPLL1_INPUT_MODE_CNFG 0X116
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#define DPLL2_INPUT_MODE_CNFG 0X196
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#define OUT_MUX_CNFG(outn) _ADDR(0x6, (0xC * (outn)))
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#define PAGE_ADDR 0x7F
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/* Register Map end */
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/* Register definitions - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf*/
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#define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
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#define SYNC_TOD BIT(1)
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#define PH_OFFSET_EN BIT(7)
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#define SQUELCH_ENABLE BIT(5)
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/* Bit definitions for the DPLL_MODE register */
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#define PLL_MODE_SHIFT (0)
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#define PLL_MODE_MASK (0x1F)
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enum pll_mode {
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PLL_MODE_MIN = 0,
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PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
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PLL_MODE_FORCE_FREERUN = 1,
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PLL_MODE_FORCE_HOLDOVER = 2,
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PLL_MODE_FORCE_LOCKED = 4,
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PLL_MODE_FORCE_PRE_LOCKED2 = 5,
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PLL_MODE_FORCE_PRE_LOCKED = 6,
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PLL_MODE_FORCE_LOST_PHASE = 7,
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PLL_MODE_DCO = 10,
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PLL_MODE_WPH = 18,
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PLL_MODE_MAX = PLL_MODE_WPH,
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};
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enum hw_tod_trig_sel {
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HW_TOD_TRIG_SEL_MIN = 0,
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HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
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HW_TOD_TRIG_SEL_SYNC_SEL = 1,
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HW_TOD_TRIG_SEL_IN12 = 2,
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HW_TOD_TRIG_SEL_IN13 = 3,
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HW_TOD_TRIG_SEL_IN14 = 4,
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HW_TOD_TRIG_SEL_TOD_PPS = 5,
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HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
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HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
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HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
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HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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};
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/* Register bit definitions end */
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#define FW_FILENAME "idt82p33xxx.bin"
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#define MAX_PHC_PLL (2)
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#define TOD_BYTE_COUNT (10)
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#define MAX_MEASURMENT_COUNT (5)
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#define SNAP_THRESHOLD_NS (150000)
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#define SYNC_TOD_TIMEOUT_SEC (5)
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#define PLLMASK_ADDR_HI 0xFF
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#define PLLMASK_ADDR_LO 0xA5
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#define PLL0_OUTMASK_ADDR_HI 0xFF
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#define PLL0_OUTMASK_ADDR_LO 0xB0
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#define PLL1_OUTMASK_ADDR_HI 0xFF
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#define PLL1_OUTMASK_ADDR_LO 0xB2
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#define PLL2_OUTMASK_ADDR_HI 0xFF
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#define PLL2_OUTMASK_ADDR_LO 0xB4
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#define PLL3_OUTMASK_ADDR_HI 0xFF
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#define PLL3_OUTMASK_ADDR_LO 0xB6
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#define DEFAULT_PLL_MASK (0x01)
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#define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
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#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
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/* PTP Hardware Clock interface */
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struct idt82p33_channel {
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struct ptp_clock_info caps;
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struct ptp_clock *ptp_clock;
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struct idt82p33 *idt82p33;
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enum pll_mode pll_mode;
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/* task to turn off SYNC_TOD bit after pps sync */
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struct delayed_work sync_tod_work;
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bool sync_tod_on;
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s32 current_freq_ppb;
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u8 output_mask;
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u16 dpll_tod_cnfg;
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u16 dpll_tod_trigger;
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u16 dpll_tod_sts;
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u16 dpll_mode_cnfg;
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u16 dpll_freq_cnfg;
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u16 dpll_phase_cnfg;
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u16 dpll_sync_cnfg;
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u16 dpll_input_mode_cnfg;
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};
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struct idt82p33 {
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struct idt82p33_channel channel[MAX_PHC_PLL];
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struct i2c_client *client;
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u8 page_offset;
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u8 pll_mask;
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ktime_t start_time;
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int calculate_overhead_flag;
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s64 tod_write_overhead_ns;
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/* Protects I2C read/modify/write registers from concurrent access */
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struct mutex reg_lock;
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};
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/* firmware interface */
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struct idt82p33_fwrc {
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u8 hiaddr;
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u8 loaddr;
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u8 value;
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u8 reserved;
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} __packed;
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/**
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* @brief Maximum absolute value for write phase offset in femtoseconds
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*/
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#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
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/** @brief Phase offset resolution
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*
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* DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
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* = 10^15 fs / ( 1638400000 * 2^23)
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* = 74.5058059692382 fs
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*/
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#define IDT_T0DPLL_PHASE_RESOL 74506
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#endif /* PTP_IDT82P33_H */
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