119 lines
3.6 KiB
ArmAsm
119 lines
3.6 KiB
ArmAsm
/*
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* Low-level user helpers placed in the vectors page for AArch32.
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* Based on the kuser helpers in arch/arm/kernel/entry-armv.S.
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*
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* Copyright (C) 2005-2011 Nicolas Pitre <nico@fluxnic.net>
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* AArch32 user helpers.
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*
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* Each segment is 32-byte aligned and will be moved to the top of the high
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* vector page. New segments (if ever needed) must be added in front of
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* existing ones. This mechanism should be used only for things that are
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* really small and justified, and not be abused freely.
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*
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* See Documentation/arm/kernel_user_helpers.txt for formal definitions.
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*/
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#include <asm/unistd.h>
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.align 5
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.globl __kuser_helper_start
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__kuser_helper_start:
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__kuser_cmpxchg64: // 0xffff0f60
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.inst 0xe92d00f0 // push {r4, r5, r6, r7}
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.inst 0xe1c040d0 // ldrd r4, r5, [r0]
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.inst 0xe1c160d0 // ldrd r6, r7, [r1]
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.inst 0xe1b20f9f // 1: ldrexd r0, r1, [r2]
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.inst 0xe0303004 // eors r3, r0, r4
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.inst 0x00313005 // eoreqs r3, r1, r5
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.inst 0x01a23e96 // stlexdeq r3, r6, [r2]
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.inst 0x03330001 // teqeq r3, #1
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.inst 0x0afffff9 // beq 1b
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.inst 0xf57ff05b // dmb ish
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.inst 0xe2730000 // rsbs r0, r3, #0
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.inst 0xe8bd00f0 // pop {r4, r5, r6, r7}
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.inst 0xe12fff1e // bx lr
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.align 5
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__kuser_memory_barrier: // 0xffff0fa0
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.inst 0xf57ff05b // dmb ish
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.inst 0xe12fff1e // bx lr
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.align 5
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__kuser_cmpxchg: // 0xffff0fc0
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.inst 0xe1923f9f // 1: ldrex r3, [r2]
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.inst 0xe0533000 // subs r3, r3, r0
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.inst 0x01823e91 // stlexeq r3, r1, [r2]
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.inst 0x03330001 // teqeq r3, #1
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.inst 0x0afffffa // beq 1b
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.inst 0xf57ff05b // dmb ish
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.inst 0xe2730000 // rsbs r0, r3, #0
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.inst 0xe12fff1e // bx lr
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.align 5
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__kuser_get_tls: // 0xffff0fe0
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.inst 0xee1d0f70 // mrc p15, 0, r0, c13, c0, 3
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.inst 0xe12fff1e // bx lr
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.rep 5
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.word 0
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.endr
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__kuser_helper_version: // 0xffff0ffc
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.word ((__kuser_helper_end - __kuser_helper_start) >> 5)
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.globl __kuser_helper_end
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__kuser_helper_end:
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/*
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* AArch32 sigreturn code
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*
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* For ARM syscalls, the syscall number has to be loaded into r7.
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* We do not support an OABI userspace.
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*
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* For Thumb syscalls, we also pass the syscall number via r7. We therefore
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* need two 16-bit instructions.
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*/
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.globl __aarch32_sigret_code_start
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__aarch32_sigret_code_start:
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/*
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* ARM Code
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*/
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.byte __NR_compat_sigreturn, 0x70, 0xa0, 0xe3 // mov r7, #__NR_compat_sigreturn
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.byte __NR_compat_sigreturn, 0x00, 0x00, 0xef // svc #__NR_compat_sigreturn
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/*
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* Thumb code
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*/
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.byte __NR_compat_sigreturn, 0x27 // svc #__NR_compat_sigreturn
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.byte __NR_compat_sigreturn, 0xdf // mov r7, #__NR_compat_sigreturn
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/*
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* ARM code
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*/
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.byte __NR_compat_rt_sigreturn, 0x70, 0xa0, 0xe3 // mov r7, #__NR_compat_rt_sigreturn
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.byte __NR_compat_rt_sigreturn, 0x00, 0x00, 0xef // svc #__NR_compat_rt_sigreturn
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/*
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* Thumb code
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*/
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.byte __NR_compat_rt_sigreturn, 0x27 // svc #__NR_compat_rt_sigreturn
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.byte __NR_compat_rt_sigreturn, 0xdf // mov r7, #__NR_compat_rt_sigreturn
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.globl __aarch32_sigret_code_end
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__aarch32_sigret_code_end:
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