240 lines
10 KiB
C
240 lines
10 KiB
C
/*----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| Author: Maciej P. Tyrlik
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| Component: Include file.
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| File: stb.h
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| Purpose: Common Set-tob-box definitions.
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| Changes:
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| Date: Comment:
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| ----- --------
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| 14-Jan-97 Created for ElPaso pass 1 MPT
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| 13-May-97 Added function prototype and global variables MPT
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| 08-Dec-98 Added RAW IR task information MPT
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| 19-Jan-99 Port to Romeo MPT
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| 19-May-00 Changed SDRAM to 32MB contiguous 0x1F000000 - 0x20FFFFFF RLB
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+----------------------------------------------------------------------------*/
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#ifndef _stb_h_
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#define _stb_h_
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/*----------------------------------------------------------------------------+
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| Read/write from I/O macros.
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+----------------------------------------------------------------------------*/
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#define inbyte(port) (*((unsigned char volatile *)(port)))
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#define outbyte(port,data) *(unsigned char volatile *)(port)=\
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(unsigned char)(data)
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#define inshort(port) (*((unsigned short volatile *)(port)))
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#define outshort(port,data) *(unsigned short volatile *)(port)=\
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(unsigned short)(data)
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#define inword(port) (*((unsigned long volatile *)(port)))
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#define outword(port,data) *(unsigned long volatile *)(port)=\
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(unsigned long)(data)
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/*----------------------------------------------------------------------------+
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| STB interrupts.
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+----------------------------------------------------------------------------*/
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#define STB_XP_TP_INT 0
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#define STB_XP_APP_INT 1
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#define STB_AUD_INT 2
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#define STB_VID_INT 3
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#define STB_DMA0_INT 4
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#define STB_DMA1_INT 5
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#define STB_DMA2_INT 6
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#define STB_DMA3_INT 7
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#define STB_SCI_INT 8
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#define STB_I2C1_INT 9
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#define STB_I2C2_INT 10
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#define STB_GPT_PWM0 11
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#define STB_GPT_PWM1 12
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#define STB_SCP_INT 13
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#define STB_SSP_INT 14
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#define STB_GPT_PWM2 15
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#define STB_EXT5_INT 16
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#define STB_EXT6_INT 17
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#define STB_EXT7_INT 18
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#define STB_EXT8_INT 19
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#define STB_SCC_INT 20
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#define STB_SICC_RECV_INT 21
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#define STB_SICC_TRAN_INT 22
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#define STB_PPU_INT 23
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#define STB_DCRX_INT 24
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#define STB_EXT0_INT 25
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#define STB_EXT1_INT 26
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#define STB_EXT2_INT 27
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#define STB_EXT3_INT 28
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#define STB_EXT4_INT 29
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#define STB_REDWOOD_ENET_INT STB_EXT1_INT
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/*----------------------------------------------------------------------------+
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| STB tasks, task stack sizes, and task priorities. The actual task priority
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| is 1 more than the specified number since priority 0 is reserved (system
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| internally adds 1 to supplied priority number).
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+----------------------------------------------------------------------------*/
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#define STB_IDLE_TASK_SS (5* 1024)
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#define STB_IDLE_TASK_PRIO 0
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#define STB_LEDTEST_SS (2* 1024)
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#define STB_LEDTEST_PRIO 0
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#define STB_CURSOR_TASK_SS (10* 1024)
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#define STB_CURSOR_TASK_PRIO 7
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#define STB_MPEG_TASK_SS (10* 1024)
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#define STB_MPEG_TASK_PRIO 9
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#define STB_DEMUX_TASK_SS (10* 1024)
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#define STB_DEMUX_TASK_PRIO 20
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#define RAW_STB_IR_TASK_SS (10* 1024)
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#define RAW_STB_IR_TASK_PRIO 20
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#define STB_SERIAL_ER_TASK_SS (10* 1024)
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#define STB_SERIAL_ER_TASK_PRIO 1
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#define STB_CA_TASK_SS (10* 1024)
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#define STB_CA_TASK_PRIO 8
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#define INIT_DEFAULT_VIDEO_SS (10* 1024)
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#define INIT_DEFAULT_VIDEO_PRIO 8
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#define INIT_DEFAULT_SERVI_SS (10* 1024)
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#define INIT_DEFAULT_SERVI_PRIO 8
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#define INIT_DEFAULT_POST_SS (10* 1024)
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#define INIT_DEFAULT_POST_PRIO 8
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#define INIT_DEFAULT_INTER_SS (10* 1024)
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#define INIT_DEFAULT_INTER_PRIO 8
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#define INIT_DEFAULT_BR_SS (10* 1024)
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#define INIT_DEFAULT_BR_PRIO 8
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#define INITIAL_TASK_STACK_SIZE (32* 1024)
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#ifdef VESTA
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/*----------------------------------------------------------------------------+
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| Vesta Overall Address Map (all addresses are double mapped, bit 0 of the
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| address is not decoded. Numbers below are dependent on board configuration.
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| FLASH, SDRAM, DRAM numbers can be affected by actual board setup.
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| FFE0,0000 - FFFF,FFFF FLASH
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| F200,0000 - F210,FFFF FPGA logic
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| Ethernet = F200,0000
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| LED Display = F200,0100
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| Xilinx #1 Regs = F204,0000
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| Xilinx #2 Regs = F208,0000
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| Spare = F20C,0000
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| IDE CS0 = F210,0000
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| F410,0000 - F410,FFFF IDE CS1
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| C000,0000 - C7FF,FFFF OBP
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| C000,0000 - C000,0014 SICC (16550 + infra red)
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| C001,0000 - C001,0018 PPU (Parallel Port)
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| C002,0000 - C002,001B SC0 (Smart Card 0)
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| C003,0000 - C003,000F I2C0
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| C004,0000 - C004,0009 SCC (16550 UART)
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| C005,0000 - C005,0124 GPT (Timers)
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| C006,0000 - C006,0058 GPIO0
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| C007,0000 - C007,001b SC1 (Smart Card 1)
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| C008,0000 - C008,FFFF Unused
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| C009,0000 - C009,FFFF Unused
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| C00A,0000 - C00A,FFFF Unused
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| C00B,0000 - C00B,000F I2C1
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| C00C,0000 - C00C,0006 SCP
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| C00D,0000 - C00D,0010 SSP
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| A000,0000 - A0FF,FFFF SDRAM1 (16M)
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| 0000,0000 - 00FF,FFFF SDRAM0 (16M)
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+----------------------------------------------------------------------------*/
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#define STB_FLASH_BASE_ADDRESS 0xFFE00000
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#define STB_FPGA_BASE_ADDRESS 0xF2000000
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#define STB_SICC_BASE_ADDRESS 0xC0000000
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#define STB_PPU_BASE_ADDR 0xC0010000
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#define STB_SC0_BASE_ADDRESS 0xC0020000
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#define STB_I2C1_BASE_ADDRESS 0xC0030000
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#define STB_SCC_BASE_ADDRESS 0xC0040000
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#define STB_TIMERS_BASE_ADDRESS 0xC0050000
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#define STB_GPIO0_BASE_ADDRESS 0xC0060000
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#define STB_SC1_BASE_ADDRESS 0xC0070000
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#define STB_I2C2_BASE_ADDRESS 0xC00B0000
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#define STB_SCP_BASE_ADDRESS 0xC00C0000
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#define STB_SSP_BASE_ADDRESS 0xC00D0000
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/*----------------------------------------------------------------------------+
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|The following are used by the IBM RTOS SW.
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|15-May-00 Changed these values to reflect movement of base addresses in
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|order to support 32MB of contiguous SDRAM space.
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|Points to the cacheable region since these values are used in IBM RTOS
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|to establish the vector address.
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+----------------------------------------------------------------------------*/
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#define STB_SDRAM1_BASE_ADDRESS 0x20000000
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#define STB_SDRAM1_SIZE 0x01000000
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#define STB_SDRAM0_BASE_ADDRESS 0x1F000000
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#define STB_SDRAM0_SIZE 0x01000000
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#else
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/*----------------------------------------------------------------------------+
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| ElPaso Overall Address Map (all addresses are double mapped, bit 0 of the
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| address is not decoded. Numbers below are dependent on board configuration.
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| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. OPB
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| devices are inside the ElPaso chip.
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| FFE0,0000 - FFFF,FFFF FLASH
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| F144,0000 - F104,FFFF FPGA logic
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| F140,0000 - F100,0000 ethernet (through FPGA logic)
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| C000,0000 - C7FF,FFFF OBP
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| C000,0000 - C000,0014 SICC (16550+ infra red)
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| C001,0000 - C001,0016 PPU (parallel port)
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| C002,0000 - C002,001B SC (smart card)
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| C003,0000 - C003,000F I2C 1
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| C004,0000 - C004,0009 SCC (16550 UART)
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| C005,0000 - C005,0124 Timers
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| C006,0000 - C006,0058 GPIO0
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| C007,0000 - C007,0058 GPIO1
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| C008,0000 - C008,0058 GPIO2
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| C009,0000 - C009,0058 GPIO3
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| C00A,0000 - C00A,0058 GPIO4
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| C00B,0000 - C00B,000F I2C 2
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| C00C,0000 - C00C,0006 SCP
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| C00D,0000 - C00D,0006 SSP
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| A000,0000 - A0FF,FFFF SDRAM 16M
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| 0000,0000 - 00FF,FFFF DRAM 16M
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+----------------------------------------------------------------------------*/
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#define STB_FLASH_BASE_ADDRESS 0xFFE00000
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#define STB_FPGA_BASE_ADDRESS 0xF1440000
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#define STB_ENET_BASE_ADDRESS 0xF1400000
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#define STB_SICC_BASE_ADDRESS 0xC0000000
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#define STB_PPU_BASE_ADDR 0xC0010000
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#define STB_SC_BASE_ADDRESS 0xC0020000
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#define STB_I2C1_BASE_ADDRESS 0xC0030000
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#define STB_SCC_BASE_ADDRESS 0xC0040000
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#define STB_TIMERS_BASE_ADDRESS 0xC0050000
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#define STB_GPIO0_BASE_ADDRESS 0xC0060000
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#define STB_GPIO1_BASE_ADDRESS 0xC0070000
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#define STB_GPIO2_BASE_ADDRESS 0xC0080000
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#define STB_GPIO3_BASE_ADDRESS 0xC0090000
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#define STB_GPIO4_BASE_ADDRESS 0xC00A0000
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#define STB_I2C2_BASE_ADDRESS 0xC00B0000
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#define STB_SCP_BASE_ADDRESS 0xC00C0000
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#define STB_SSP_BASE_ADDRESS 0xC00D0000
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#define STB_SDRAM_BASE_ADDRESS 0xA0000000
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#endif
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/*----------------------------------------------------------------------------+
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| Other common defines.
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+----------------------------------------------------------------------------*/
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#endif /* _stb_h_ */
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