279 lines
6.5 KiB
C
279 lines
6.5 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define PLL_NPLL 5
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/* sclk gates (special clocks) */
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#define SCLK_GPU 64
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#define SCLK_SPI0 65
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#define SCLK_SPI1 66
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#define SCLK_SPI2 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO0 69
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#define SCLK_SDIO1 70
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#define SCLK_EMMC 71
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#define SCLK_TSADC 72
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#define SCLK_SARADC 73
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#define SCLK_PS2C 74
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#define SCLK_NANDC0 75
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#define SCLK_NANDC1 76
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_UART3 80
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#define SCLK_UART4 81
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#define SCLK_I2S0 82
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#define SCLK_SPDIF 83
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#define SCLK_SPDIF8CH 84
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_TIMER4 89
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#define SCLK_TIMER5 90
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#define SCLK_TIMER6 91
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#define SCLK_HSADC 92
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#define SCLK_OTGPHY0 93
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#define SCLK_OTGPHY1 94
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#define SCLK_OTGPHY2 95
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#define SCLK_OTG_ADP 96
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#define SCLK_HSICPHY480M 97
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#define SCLK_HSICPHY12M 98
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#define SCLK_MACREF 99
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#define SCLK_LCDC_PWM0 100
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#define SCLK_LCDC_PWM1 101
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#define SCLK_MAC_RX 102
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#define SCLK_MAC_TX 103
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#define DCLK_VOP0 190
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#define DCLK_VOP1 191
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/* aclk gates */
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#define ACLK_GPU 192
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#define ACLK_DMAC1 193
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#define ACLK_DMAC2 194
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#define ACLK_MMU 195
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#define ACLK_GMAC 196
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#define ACLK_VOP0 197
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#define ACLK_VOP1 198
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#define ACLK_CRYPTO 199
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#define ACLK_RGA 200
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_GPIO4 324
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#define PCLK_GPIO5 325
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#define PCLK_GPIO6 326
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#define PCLK_GPIO7 327
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#define PCLK_GPIO8 328
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#define PCLK_GRF 329
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#define PCLK_SGRF 330
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#define PCLK_PMU 331
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
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#define PCLK_I2C4 336
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#define PCLK_I2C5 337
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#define PCLK_SPI0 338
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#define PCLK_SPI1 339
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#define PCLK_SPI2 340
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_UART3 344
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#define PCLK_UART4 345
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#define PCLK_TSADC 346
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#define PCLK_SARADC 347
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#define PCLK_SIM 348
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#define PCLK_GMAC 349
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#define PCLK_PWM 350
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#define PCLK_RKPWM 351
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#define PCLK_PS2C 352
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#define PCLK_TIMER 353
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#define PCLK_TZPC 354
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/* hclk gates */
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#define HCLK_GPS 448
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#define HCLK_OTG0 449
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#define HCLK_USBHOST0 450
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#define HCLK_USBHOST1 451
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#define HCLK_HSIC 452
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#define HCLK_NANDC0 453
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#define HCLK_NANDC1 454
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#define HCLK_TSP 455
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#define HCLK_SDMMC 456
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#define HCLK_SDIO0 457
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#define HCLK_SDIO1 458
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#define HCLK_EMMC 459
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#define HCLK_HSADC 460
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#define HCLK_CRYPTO 461
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#define HCLK_I2S0 462
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#define HCLK_SPDIF 463
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#define HCLK_SPDIF8CH 464
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#define HCLK_VOP0 465
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#define HCLK_VOP1 466
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#define HCLK_ROM 467
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#define HCLK_IEP 468
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#define HCLK_ISP 469
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#define HCLK_RGA 470
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#define CLK_NR_CLKS (HCLK_RGA + 1)
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/* soft-reset indices */
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#define SRST_CORE0 0
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#define SRST_CORE1 1
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#define SRST_CORE2 2
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#define SRST_CORE3 3
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#define SRST_CORE0_PO 4
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#define SRST_CORE1_PO 5
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#define SRST_CORE2_PO 6
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#define SRST_CORE3_PO 7
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#define SRST_PDCORE_STRSYS 8
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#define SRST_PDBUS_STRSYS 9
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#define SRST_L2C 10
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#define SRST_TOPDBG 11
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#define SRST_CORE0_DBG 12
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#define SRST_CORE1_DBG 13
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#define SRST_CORE2_DBG 14
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#define SRST_CORE3_DBG 15
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#define SRST_PDBUG_AHB_ARBITOR 16
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#define SRST_EFUSE256 17
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#define SRST_DMAC1 18
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#define SRST_INTMEM 19
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#define SRST_ROM 20
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#define SRST_SPDIF8CH 21
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#define SRST_TIMER 22
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#define SRST_I2S0 23
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#define SRST_SPDIF 24
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#define SRST_TIMER0 25
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#define SRST_TIMER1 26
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#define SRST_TIMER2 27
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#define SRST_TIMER3 28
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#define SRST_TIMER4 29
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#define SRST_TIMER5 30
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#define SRST_EFUSE 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_GPIO4 36
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#define SRST_GPIO5 37
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#define SRST_GPIO6 38
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#define SRST_GPIO7 39
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#define SRST_GPIO8 40
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#define SRST_I2C0 42
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#define SRST_I2C1 43
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#define SRST_I2C2 44
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#define SRST_I2C3 45
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#define SRST_I2C4 46
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#define SRST_I2C5 47
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#define SRST_DWPWM 48
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#define SRST_MMC_PERI 49
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#define SRST_PERIPH_MMU 50
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#define SRST_DAP 51
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#define SRST_DAP_SYS 52
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#define SRST_TPIU 53
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#define SRST_PMU_APB 54
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#define SRST_GRF 55
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#define SRST_PMU 56
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#define SRST_PERIPH_AXI 57
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#define SRST_PERIPH_AHB 58
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#define SRST_PERIPH_APB 59
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#define SRST_PERIPH_NIU 60
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#define SRST_PDPERI_AHB_ARBI 61
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#define SRST_EMEM 62
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#define SRST_USB_PERI 63
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#define SRST_DMAC2 64
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#define SRST_MAC 66
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#define SRST_GPS 67
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#define SRST_RKPWM 69
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#define SRST_CCP 71
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#define SRST_USBHOST0 72
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#define SRST_HSIC 73
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#define SRST_HSIC_AUX 74
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#define SRST_HSIC_PHY 75
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#define SRST_HSADC 76
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#define SRST_NANDC0 77
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#define SRST_NANDC1 78
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#define SRST_TZPC 80
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#define SRST_SPI0 83
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#define SRST_SPI1 84
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#define SRST_SPI2 85
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#define SRST_SARADC 87
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#define SRST_PDALIVE_NIU 88
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#define SRST_PDPMU_INTMEM 89
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#define SRST_PDPMU_NIU 90
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#define SRST_SGRF 91
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#define SRST_VIO_ARBI 96
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#define SRST_RGA_NIU 97
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#define SRST_VIO0_NIU_AXI 98
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#define SRST_VIO_NIU_AHB 99
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#define SRST_LCDC0_AXI 100
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#define SRST_LCDC0_AHB 101
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#define SRST_LCDC0_DCLK 102
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#define SRST_VIO1_NIU_AXI 103
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#define SRST_VIP 104
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#define SRST_RGA_CORE 105
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#define SRST_IEP_AXI 106
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#define SRST_IEP_AHB 107
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#define SRST_RGA_AXI 108
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#define SRST_RGA_AHB 109
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#define SRST_ISP 110
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#define SRST_EDP 111
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#define SRST_VCODEC_AXI 112
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#define SRST_VCODEC_AHB 113
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#define SRST_VIO_H2P 114
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#define SRST_MIPIDSI0 115
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#define SRST_MIPIDSI1 116
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#define SRST_MIPICSI 117
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#define SRST_LVDS_PHY 118
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#define SRST_LVDS_CON 119
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#define SRST_GPU 120
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#define SRST_HDMI 121
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#define SRST_CORE_PVTM 124
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#define SRST_GPU_PVTM 125
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#define SRST_MMC0 128
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#define SRST_SDIO0 129
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#define SRST_SDIO1 130
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#define SRST_EMMC 131
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#define SRST_USBOTG_AHB 132
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#define SRST_USBOTG_PHY 133
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#define SRST_USBOTG_CON 134
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#define SRST_USBHOST0_AHB 135
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#define SRST_USBHOST0_PHY 136
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#define SRST_USBHOST0_CON 137
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#define SRST_USBHOST1_AHB 138
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#define SRST_USBHOST1_PHY 139
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#define SRST_USBHOST1_CON 140
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#define SRST_USB_ADP 141
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#define SRST_ACC_EFUSE 142
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