155 lines
4.3 KiB
C
155 lines
4.3 KiB
C
/*
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* arch/arm/mach-orion5x/addr-map.c
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*
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* Address map functions for Marvell Orion 5x SoCs
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <plat/addr-map.h>
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#include "common.h"
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/*
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* The Orion has fully programmable address map. There's a separate address
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* map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
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* Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
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* address decode windows that allow it to access any of the Orion resources.
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*
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* CPU address decoding --
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* Linux assumes that it is the boot loader that already setup the access to
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* DDR and internal registers.
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* Setup access to PCI and PCIe IO/MEM space is issued by this file.
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* Setup access to various devices located on the device bus interface (e.g.
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* flashes, RTC, etc) should be issued by machine-setup.c according to
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* specific board population (by using orion5x_setup_*_win()).
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*
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* Non-CPU Masters address decoding --
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* Unlike the CPU, we setup the access from Orion's master interfaces to DDR
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* banks only (the typical use case).
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* Setup access for each master to DDR is issued by platform device setup.
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*/
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DEV_BUS 1
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#define TARGET_PCI 3
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#define TARGET_PCIE 4
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#define TARGET_SRAM 9
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#define ATTR_PCIE_MEM 0x59
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#define ATTR_PCIE_IO 0x51
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#define ATTR_PCIE_WA 0x79
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#define ATTR_PCI_MEM 0x59
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#define ATTR_PCI_IO 0x51
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#define ATTR_DEV_CS0 0x1e
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#define ATTR_DEV_CS1 0x1d
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#define ATTR_DEV_CS2 0x1b
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#define ATTR_DEV_BOOT 0xf
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#define ATTR_SRAM 0x0
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static int __initdata win_alloc_count;
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static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
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const int win)
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{
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u32 dev, rev;
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orion5x_pcie_id(&dev, &rev);
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if ((dev == MV88F5281_DEV_ID && win < 4)
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|| (dev == MV88F5182_DEV_ID && win < 2)
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|| (dev == MV88F5181_DEV_ID && win < 2)
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|| (dev == MV88F6183_DEV_ID && win < 4))
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return 1;
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return 0;
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}
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/*
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* Description of the windows needed by the platform code
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*/
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static struct __initdata orion_addr_map_cfg addr_map_cfg = {
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.num_wins = 8,
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.cpu_win_can_remap = cpu_win_can_remap,
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.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
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};
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static const struct __initdata orion_addr_map_info addr_map_info[] = {
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/*
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* Setup windows for PCI+PCIe IO+MEM space.
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*/
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{ 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
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},
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{ 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
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TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
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},
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{ 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE_MEM, -1
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},
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{ 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
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TARGET_PCI, ATTR_PCI_MEM, -1
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},
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/* End marker */
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{ -1, 0, 0, 0, 0, 0 }
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};
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void __init orion5x_setup_cpu_mbus_bridge(void)
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{
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/*
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* Disable, clear and configure windows.
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*/
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orion_config_wins(&addr_map_cfg, addr_map_info);
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win_alloc_count = 4;
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/*
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* Setup MBUS dram target info.
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*/
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orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
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}
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void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
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{
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orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
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TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
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}
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void __init orion5x_setup_dev0_win(u32 base, u32 size)
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{
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orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
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TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
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}
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void __init orion5x_setup_dev1_win(u32 base, u32 size)
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{
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orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
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TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
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}
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void __init orion5x_setup_dev2_win(u32 base, u32 size)
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{
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orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
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TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
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}
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void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
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{
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orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
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TARGET_PCIE, ATTR_PCIE_WA, -1);
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}
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void __init orion5x_setup_sram_win(void)
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{
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orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
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ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
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TARGET_SRAM, ATTR_SRAM, -1);
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}
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