98 lines
4.0 KiB
ReStructuredText
98 lines
4.0 KiB
ReStructuredText
When do you need to notify inside page table lock ?
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===================================================
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When clearing a pte/pmd we are given a choice to notify the event through
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(notify version of \*_clear_flush call mmu_notifier_invalidate_range) under
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the page table lock. But that notification is not necessary in all cases.
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For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
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thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
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process virtual address space). There is only 2 cases when you need to notify
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those secondary TLB while holding page table lock when clearing a pte/pmd:
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A) page backing address is free before mmu_notifier_invalidate_range_end()
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B) a page table entry is updated to point to a new page (COW, write fault
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on zero page, __replace_page(), ...)
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Case A is obvious you do not want to take the risk for the device to write to
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a page that might now be used by some completely different task.
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Case B is more subtle. For correctness it requires the following sequence to
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happen:
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- take page table lock
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- clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
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- set page table entry to point to new page
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If clearing the page table entry is not followed by a notify before setting
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the new pte/pmd value then you can break memory model like C11 or C++11 for
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the device.
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Consider the following scenario (device use a feature similar to ATS/PASID):
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Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
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they are write protected for COW (other case of B apply too).
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::
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[Time N] --------------------------------------------------------------------
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CPU-thread-0 {try to write to addrA}
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CPU-thread-1 {try to write to addrB}
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CPU-thread-2 {}
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CPU-thread-3 {}
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DEV-thread-0 {read addrA and populate device TLB}
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DEV-thread-2 {read addrB and populate device TLB}
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[Time N+1] ------------------------------------------------------------------
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CPU-thread-0 {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
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CPU-thread-1 {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
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CPU-thread-2 {}
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CPU-thread-3 {}
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DEV-thread-0 {}
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DEV-thread-2 {}
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[Time N+2] ------------------------------------------------------------------
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CPU-thread-0 {COW_step1: {update page table to point to new page for addrA}}
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CPU-thread-1 {COW_step1: {update page table to point to new page for addrB}}
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CPU-thread-2 {}
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CPU-thread-3 {}
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DEV-thread-0 {}
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DEV-thread-2 {}
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[Time N+3] ------------------------------------------------------------------
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CPU-thread-0 {preempted}
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CPU-thread-1 {preempted}
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CPU-thread-2 {write to addrA which is a write to new page}
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CPU-thread-3 {}
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DEV-thread-0 {}
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DEV-thread-2 {}
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[Time N+3] ------------------------------------------------------------------
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CPU-thread-0 {preempted}
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CPU-thread-1 {preempted}
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CPU-thread-2 {}
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CPU-thread-3 {write to addrB which is a write to new page}
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DEV-thread-0 {}
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DEV-thread-2 {}
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[Time N+4] ------------------------------------------------------------------
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CPU-thread-0 {preempted}
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CPU-thread-1 {COW_step3: {mmu_notifier_invalidate_range_end(addrB)}}
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CPU-thread-2 {}
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CPU-thread-3 {}
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DEV-thread-0 {}
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DEV-thread-2 {}
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[Time N+5] ------------------------------------------------------------------
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CPU-thread-0 {preempted}
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CPU-thread-1 {}
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CPU-thread-2 {}
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CPU-thread-3 {}
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DEV-thread-0 {read addrA from old page}
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DEV-thread-2 {read addrB from new page}
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So here because at time N+2 the clear page table entry was not pair with a
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notification to invalidate the secondary TLB, the device see the new value for
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addrB before seeing the new value for addrA. This break total memory ordering
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for the device.
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When changing a pte to write protect or to point to a new write protected page
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with same content (KSM) it is fine to delay the mmu_notifier_invalidate_range
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call to mmu_notifier_invalidate_range_end() outside the page table lock. This
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is true even if the thread doing the page table update is preempted right after
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releasing page table lock but before call mmu_notifier_invalidate_range_end().
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