428 lines
9.6 KiB
C
428 lines
9.6 KiB
C
/*
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*
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* Intel Management Engine Interface (Intel MEI) Linux driver
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* Copyright (c) 2003-2012, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/pci.h>
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#include <linux/mei.h>
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#include "mei_dev.h"
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#include "hw-me.h"
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/**
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* mei_reg_read - Reads 32bit data from the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to read the data
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*
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* returns register value (u32)
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*/
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static inline u32 mei_reg_read(const struct mei_me_hw *hw,
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unsigned long offset)
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{
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return ioread32(hw->mem_addr + offset);
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}
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/**
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* mei_reg_write - Writes 32bit data to the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to write the data
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* @value: register value to write (u32)
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*/
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static inline void mei_reg_write(const struct mei_me_hw *hw,
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unsigned long offset, u32 value)
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{
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iowrite32(value, hw->mem_addr + offset);
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}
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/**
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* mei_mecbrw_read - Reads 32bit data from ME circular buffer
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* read window register
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*
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* @dev: the device structure
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*
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* returns ME_CB_RW register value (u32)
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*/
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u32 mei_mecbrw_read(const struct mei_device *dev)
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{
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return mei_reg_read(to_me_hw(dev), ME_CB_RW);
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}
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/**
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* mei_mecsr_read - Reads 32bit data from the ME CSR
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*
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* @dev: the device structure
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*
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* returns ME_CSR_HA register value (u32)
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*/
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static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
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{
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return mei_reg_read(hw, ME_CSR_HA);
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}
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/**
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* mei_hcsr_read - Reads 32bit data from the host CSR
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*
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* @dev: the device structure
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*
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* returns H_CSR register value (u32)
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*/
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static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
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{
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return mei_reg_read(hw, H_CSR);
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}
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/**
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* mei_hcsr_set - writes H_CSR register to the mei device,
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* and ignores the H_IS bit for it is write-one-to-zero.
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*
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* @dev: the device structure
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*/
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static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
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{
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hcsr &= ~H_IS;
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mei_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* me_hw_config - configure hw dependent settings
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*
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* @dev: mei device
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*/
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void mei_hw_config(struct mei_device *dev)
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{
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u32 hcsr = mei_hcsr_read(to_me_hw(dev));
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/* Doesn't change in runtime */
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dev->hbuf_depth = (hcsr & H_CBD) >> 24;
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}
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/**
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* mei_clear_interrupts - clear and stop interrupts
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*
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* @dev: the device structure
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*/
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void mei_clear_interrupts(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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if ((hcsr & H_IS) == H_IS)
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mei_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* mei_enable_interrupts - enables mei device interrupts
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*
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* @dev: the device structure
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*/
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void mei_enable_interrupts(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr |= H_IE;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* mei_disable_interrupts - disables mei device interrupts
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*
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* @dev: the device structure
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*/
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void mei_disable_interrupts(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr &= ~H_IE;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* mei_hw_reset - resets fw via mei csr register.
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*
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* @dev: the device structure
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* @interrupts_enabled: if interrupt should be enabled after reset.
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*/
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void mei_hw_reset(struct mei_device *dev, bool intr_enable)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr);
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hcsr |= (H_RST | H_IG);
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if (intr_enable)
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hcsr |= H_IE;
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else
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hcsr &= ~H_IE;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(hw) | H_IG;
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hcsr &= ~H_RST;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(hw);
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dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
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}
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/**
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* mei_host_set_ready - enable device
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*
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* @dev - mei device
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* returns bool
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*/
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void mei_host_set_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->host_hw_state |= H_IE | H_IG | H_RDY;
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mei_hcsr_set(hw, hw->host_hw_state);
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}
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/**
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* mei_host_is_ready - check whether the host has turned ready
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*
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* @dev - mei device
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* returns bool
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*/
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bool mei_host_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->host_hw_state = mei_hcsr_read(hw);
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return (hw->host_hw_state & H_RDY) == H_RDY;
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}
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/**
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* mei_me_is_ready - check whether the me has turned ready
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*
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* @dev - mei device
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* returns bool
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*/
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bool mei_me_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->me_hw_state = mei_mecsr_read(hw);
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return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
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}
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/**
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* mei_interrupt_quick_handler - The ISR of the MEI device
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*
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* @irq: The irq number
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* @dev_id: pointer to the device structure
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*
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* returns irqreturn_t
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*/
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irqreturn_t mei_interrupt_quick_handler(int irq, void *dev_id)
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{
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struct mei_device *dev = (struct mei_device *) dev_id;
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 csr_reg = mei_hcsr_read(hw);
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if ((csr_reg & H_IS) != H_IS)
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return IRQ_NONE;
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/* clear H_IS bit in H_CSR */
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mei_reg_write(hw, H_CSR, csr_reg);
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return IRQ_WAKE_THREAD;
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}
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/**
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* mei_hbuf_filled_slots - gets number of device filled buffer slots
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*
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* @dev: the device structure
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*
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* returns number of filled slots
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*/
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static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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char read_ptr, write_ptr;
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hw->host_hw_state = mei_hcsr_read(hw);
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read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
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write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
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return (unsigned char) (write_ptr - read_ptr);
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}
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/**
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* mei_hbuf_is_empty - checks if host buffer is empty.
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*
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* @dev: the device structure
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*
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* returns true if empty, false - otherwise.
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*/
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bool mei_hbuf_is_empty(struct mei_device *dev)
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{
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return mei_hbuf_filled_slots(dev) == 0;
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}
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/**
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* mei_hbuf_empty_slots - counts write empty slots.
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*
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* @dev: the device structure
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*
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* returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
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*/
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int mei_hbuf_empty_slots(struct mei_device *dev)
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{
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unsigned char filled_slots, empty_slots;
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filled_slots = mei_hbuf_filled_slots(dev);
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empty_slots = dev->hbuf_depth - filled_slots;
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/* check for overflow */
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if (filled_slots > dev->hbuf_depth)
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return -EOVERFLOW;
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return empty_slots;
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}
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/**
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* mei_write_message - writes a message to mei device.
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*
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* @dev: the device structure
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* @header: mei HECI header of message
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* @buf: message payload will be written
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*
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* This function returns -EIO if write has failed
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*/
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int mei_write_message(struct mei_device *dev, struct mei_msg_hdr *header,
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unsigned char *buf)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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unsigned long rem, dw_cnt;
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unsigned long length = header->length;
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u32 *reg_buf = (u32 *)buf;
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u32 hcsr;
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int i;
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int empty_slots;
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dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
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empty_slots = mei_hbuf_empty_slots(dev);
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dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
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dw_cnt = mei_data2slots(length);
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if (empty_slots < 0 || dw_cnt > empty_slots)
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return -EIO;
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mei_reg_write(hw, H_CB_WW, *((u32 *) header));
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for (i = 0; i < length / 4; i++)
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mei_reg_write(hw, H_CB_WW, reg_buf[i]);
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rem = length & 0x3;
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if (rem > 0) {
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u32 reg = 0;
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memcpy(®, &buf[length - rem], rem);
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mei_reg_write(hw, H_CB_WW, reg);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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if (!mei_me_is_ready(dev))
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return -EIO;
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return 0;
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}
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/**
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* mei_count_full_read_slots - counts read full slots.
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*
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* @dev: the device structure
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*
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* returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
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*/
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int mei_count_full_read_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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char read_ptr, write_ptr;
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unsigned char buffer_depth, filled_slots;
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hw->me_hw_state = mei_mecsr_read(hw);
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buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
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read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
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write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
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filled_slots = (unsigned char) (write_ptr - read_ptr);
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/* check for overflow */
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if (filled_slots > buffer_depth)
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return -EOVERFLOW;
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dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
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return (int)filled_slots;
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}
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/**
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* mei_read_slots - reads a message from mei device.
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*
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* @dev: the device structure
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* @buffer: message buffer will be written
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* @buffer_length: message size will be read
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*/
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void mei_read_slots(struct mei_device *dev, unsigned char *buffer,
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unsigned long buffer_length)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 *reg_buf = (u32 *)buffer;
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u32 hcsr;
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for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
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*reg_buf++ = mei_mecbrw_read(dev);
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if (buffer_length > 0) {
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u32 reg = mei_mecbrw_read(dev);
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memcpy(reg_buf, ®, buffer_length);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* init_mei_device - allocates and initializes the mei device structure
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*
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* @pdev: The pci device structure
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*
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* returns The mei_device_device pointer on success, NULL on failure.
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*/
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struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
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{
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struct mei_device *dev;
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dev = kzalloc(sizeof(struct mei_device) +
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sizeof(struct mei_me_hw), GFP_KERNEL);
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if (!dev)
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return NULL;
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mei_device_init(dev);
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INIT_LIST_HEAD(&dev->wd_cl.link);
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INIT_LIST_HEAD(&dev->iamthif_cl.link);
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mei_io_list_init(&dev->amthif_cmd_list);
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mei_io_list_init(&dev->amthif_rd_complete_list);
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INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
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INIT_WORK(&dev->init_work, mei_host_client_init);
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dev->pdev = pdev;
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return dev;
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}
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