112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
/*
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* arch/ppc/platforms/4xx/yucca.h
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*
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* Yucca board definitions
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*
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* Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
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*
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* Copyright 2004-2005 MontaVista Software Inc.
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_YUCCA_H__
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#define __ASM_YUCCA_H__
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#include <linux/config.h>
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#include <platforms/4xx/ppc440spe.h>
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/* F/W TLB mapping used in bootloader glue to reset EMAC */
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#define PPC44x_EMAC0_MR0 0xa0000800
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/* Location of MAC addresses in PIBS image */
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#define PIBS_FLASH_BASE 0xffe00000
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#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
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/* External timer clock frequency */
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#define YUCCA_TMR_CLK 25000000
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/*
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* FPGA registers
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*/
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#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL
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#define YUCCA_FPGA_REG_SIZE 0x24
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#define FPGA_REG1A 0x1a
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#define FPGA_REG1A_PE0_GLED 0x8000
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#define FPGA_REG1A_PE1_GLED 0x4000
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#define FPGA_REG1A_PE2_GLED 0x2000
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#define FPGA_REG1A_PE0_YLED 0x1000
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#define FPGA_REG1A_PE1_YLED 0x0800
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#define FPGA_REG1A_PE2_YLED 0x0400
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#define FPGA_REG1A_PE0_PWRON 0x0200
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#define FPGA_REG1A_PE1_PWRON 0x0100
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#define FPGA_REG1A_PE2_PWRON 0x0080
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#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
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#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
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#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
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#define FPGA_REG1A_PE_SPREAD0 0x0008
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#define FPGA_REG1A_PE_SPREAD1 0x0004
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#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
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#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
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#define FPGA_REG1C 0x1c
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#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
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#define FPGA_REG1C_PE1_ENDPOINT 0x4000
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#define FPGA_REG1C_PE2_ENDPOINT 0x2000
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#define FPGA_REG1C_PE0_PRSNT 0x1000
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#define FPGA_REG1C_PE1_PRSNT 0x0800
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#define FPGA_REG1C_PE2_PRSNT 0x0400
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#define FPGA_REG1C_PE0_WAKE 0x0080
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#define FPGA_REG1C_PE1_WAKE 0x0040
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#define FPGA_REG1C_PE2_WAKE 0x0020
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#define FPGA_REG1C_PE0_PERST 0x0010
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#define FPGA_REG1C_PE1_PERST 0x0008
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#define FPGA_REG1C_PE2_PERST 0x0004
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/*
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* Serial port defines
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*/
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#define RS_TABLE_SIZE 3
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/* PIBS defined UART mappings, used before early_serial_setup */
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#define UART0_IO_BASE 0xa0000200
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#define UART1_IO_BASE 0xa0000300
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#define UART2_IO_BASE 0xa0000600
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#define BASE_BAUD 11059200
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#define STD_UART_OP(num) \
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{ 0, BASE_BAUD, 0, UART##num##_INT, \
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(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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iomem_base: (void*)UART##num##_IO_BASE, \
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io_type: SERIAL_IO_MEM},
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(0) \
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STD_UART_OP(1) \
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STD_UART_OP(2)
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/* PCI support */
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#define YUCCA_PCIX_LOWER_IO 0x00000000
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#define YUCCA_PCIX_UPPER_IO 0x0000ffff
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#define YUCCA_PCIX_LOWER_MEM 0x80000000
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#define YUCCA_PCIX_UPPER_MEM 0x8fffffff
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#define YUCCA_PCIE_LOWER_MEM 0x90000000
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#define YUCCA_PCIE_MEM_SIZE 0x10000000
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#define YUCCA_PCIX_MEM_SIZE 0x10000000
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#define YUCCA_PCIX_MEM_OFFSET 0x00000000
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#define YUCCA_PCIE_MEM_SIZE 0x10000000
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#define YUCCA_PCIE_MEM_OFFSET 0x00000000
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#endif /* __ASM_YUCCA_H__ */
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#endif /* __KERNEL__ */
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