294 lines
6.2 KiB
ArmAsm
294 lines
6.2 KiB
ArmAsm
/*
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* arch/ppc/boot/common/util.S
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*
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* Useful bootup functions, which are more easily done in asm than C.
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*
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* NOTE: Be very very careful about the registers you use here.
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* We don't follow any ABI calling convention among the
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* assembler functions that call each other, especially early
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* in the initialization. Please preserve at least r3 and r4
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* for these early functions, as they often contain information
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* passed from boot roms into the C decompress function.
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*
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* Author: Tom Rini
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* trini@mvista.com
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* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/ppc_asm.h>
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.text
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#ifdef CONFIG_6xx
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.globl disable_6xx_mmu
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disable_6xx_mmu:
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/* Establish default MSR value, exception prefix 0xFFF.
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* If necessary, this function must fix up the LR if we
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* return to a different address space once the MMU is
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* disabled.
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*/
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li r8,MSR_IP|MSR_FP
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mtmsr r8
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isync
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/* Test for a 601 */
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mfpvr r10
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srwi r10,r10,16
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cmpwi 0,r10,1 /* 601 ? */
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beq .clearbats_601
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/* Clear BATs */
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li r8,0
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mtspr SPRN_DBAT0U,r8
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mtspr SPRN_DBAT0L,r8
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mtspr SPRN_DBAT1U,r8
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mtspr SPRN_DBAT1L,r8
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mtspr SPRN_DBAT2U,r8
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mtspr SPRN_DBAT2L,r8
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mtspr SPRN_DBAT3U,r8
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mtspr SPRN_DBAT3L,r8
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.clearbats_601:
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mtspr SPRN_IBAT0U,r8
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mtspr SPRN_IBAT0L,r8
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mtspr SPRN_IBAT1U,r8
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mtspr SPRN_IBAT1L,r8
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mtspr SPRN_IBAT2U,r8
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mtspr SPRN_IBAT2L,r8
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mtspr SPRN_IBAT3U,r8
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mtspr SPRN_IBAT3L,r8
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isync
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sync
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sync
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/* Set segment registers */
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li r8,16 /* load up segment register values */
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mtctr r8 /* for context 0 */
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lis r8,0x2000 /* Ku = 1, VSID = 0 */
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li r10,0
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3: mtsrin r8,r10
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addi r8,r8,0x111 /* increment VSID */
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addis r10,r10,0x1000 /* address of next segment */
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bdnz 3b
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blr
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.globl disable_6xx_l1cache
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disable_6xx_l1cache:
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/* Enable, invalidate and then disable the L1 icache/dcache. */
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li r8,0
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ori r8,r8,(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
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mfspr r11,SPRN_HID0
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or r11,r11,r8
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andc r10,r11,r8
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isync
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mtspr SPRN_HID0,r8
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sync
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isync
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mtspr SPRN_HID0,r10
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sync
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isync
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blr
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#endif
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.globl _setup_L2CR
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_setup_L2CR:
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/*
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* We should be skipping this section on CPUs where this results in an
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* illegal instruction. If not, please send trini@kernel.crashing.org
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* the PVR of your CPU.
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*/
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/* Invalidate/disable L2 cache */
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sync
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isync
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mfspr r8,SPRN_L2CR
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rlwinm r8,r8,0,1,31
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oris r8,r8,L2CR_L2I@h
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sync
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isync
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mtspr SPRN_L2CR,r8
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sync
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isync
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/* Wait for the invalidation to complete */
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mfspr r8,SPRN_PVR
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srwi r8,r8,16
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cmplwi cr0,r8,0x8000 /* 7450 */
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cmplwi cr1,r8,0x8001 /* 7455 */
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cmplwi cr2,r8,0x8002 /* 7457 */
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cror 4*cr0+eq,4*cr0+eq,4*cr1+eq /* Now test if any are true. */
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cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
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bne 2f
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1: mfspr r8,SPRN_L2CR /* On 745x, poll L2I bit (bit 10) */
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rlwinm. r9,r8,0,10,10
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bne 1b
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b 3f
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2: mfspr r8,SPRN_L2CR /* On 75x & 74[01]0, poll L2IP bit (bit 31) */
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rlwinm. r9,r8,0,31,31
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bne 2b
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3: rlwinm r8,r8,0,11,9 /* Turn off L2I bit */
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sync
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isync
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mtspr SPRN_L2CR,r8
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sync
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isync
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blr
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.globl _setup_L3CR
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_setup_L3CR:
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/* Invalidate/disable L3 cache */
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sync
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isync
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mfspr r8,SPRN_L3CR
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rlwinm r8,r8,0,1,31
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ori r8,r8,L3CR_L3I@l
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sync
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isync
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mtspr SPRN_L3CR,r8
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sync
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isync
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/* Wait for the invalidation to complete */
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1: mfspr r8,SPRN_L3CR
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rlwinm. r9,r8,0,21,21
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bne 1b
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rlwinm r8,r8,0,22,20 /* Turn off L3I bit */
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sync
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isync
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mtspr SPRN_L3CR,r8
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sync
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isync
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blr
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/* udelay (on non-601 processors) needs to know the period of the
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* timebase in nanoseconds. This used to be hardcoded to be 60ns
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* (period of 66MHz/4). Now a variable is used that is initialized to
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* 60 for backward compatibility, but it can be overridden as necessary
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* with code something like this:
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* extern unsigned long timebase_period_ns;
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* timebase_period_ns = 1000000000 / bd->bi_tbfreq;
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*/
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.data
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.globl timebase_period_ns
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timebase_period_ns:
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.long 60
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.text
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/*
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* Delay for a number of microseconds
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*/
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.globl udelay
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udelay:
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mfspr r4,SPRN_PVR
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srwi r4,r4,16
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cmpwi 0,r4,1 /* 601 ? */
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bne .udelay_not_601
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00: li r0,86 /* Instructions / microsecond? */
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mtctr r0
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10: addi r0,r0,0 /* NOP */
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bdnz 10b
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subic. r3,r3,1
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bne 00b
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blr
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.udelay_not_601:
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mulli r4,r3,1000 /* nanoseconds */
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/* Change r4 to be the number of ticks using:
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* (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns
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* timebase_period_ns defaults to 60 (16.6MHz) */
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lis r5,timebase_period_ns@ha
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lwz r5,timebase_period_ns@l(r5)
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add r4,r4,r5
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addi r4,r4,-1
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divw r4,r4,r5 /* BUS ticks */
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1: mftbu r5
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mftb r6
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mftbu r7
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cmpw 0,r5,r7
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bne 1b /* Get [synced] base time */
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addc r9,r6,r4 /* Compute end time */
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addze r8,r5
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2: mftbu r5
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cmpw 0,r5,r8
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blt 2b
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bgt 3f
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mftb r6
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cmpw 0,r6,r9
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blt 2b
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3: blr
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.section ".relocate_code","xa"
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/*
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* Flush and enable instruction cache
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* First, flush the data cache in case it was enabled and may be
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* holding instructions for copy back.
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*/
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_GLOBAL(flush_instruction_cache)
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mflr r6
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bl flush_data_cache
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#ifdef CONFIG_8xx
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lis r3, IDC_INVALL@h
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mtspr SPRN_IC_CST, r3
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lis r3, IDC_ENABLE@h
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mtspr SPRN_IC_CST, r3
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lis r3, IDC_DISABLE@h
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mtspr SPRN_DC_CST, r3
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#elif CONFIG_4xx
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lis r3,start@h # r9 = &_start
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lis r4,_etext@ha
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addi r4,r4,_etext@l # r8 = &_etext
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1: dcbf r0,r3 # Flush the data cache
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icbi r0,r3 # Invalidate the instruction cache
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addi r3,r3,0x10 # Increment by one cache line
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cmplwi cr0,r3,r4 # Are we at the end yet?
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blt 1b # No, keep flushing and invalidating
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#else
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/* Enable, invalidate and then disable the L1 icache/dcache. */
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li r3,0
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ori r3,r3,(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
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mfspr r4,SPRN_HID0
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or r5,r4,r3
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isync
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mtspr SPRN_HID0,r5
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sync
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isync
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ori r5,r4,HID0_ICE /* Enable cache */
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mtspr SPRN_HID0,r5
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sync
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isync
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#endif
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mtlr r6
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blr
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#define NUM_CACHE_LINES 128*8
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#define cache_flush_buffer 0x1000
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/*
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* Flush data cache
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* Do this by just reading lots of stuff into the cache.
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*/
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_GLOBAL(flush_data_cache)
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lis r3,cache_flush_buffer@h
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ori r3,r3,cache_flush_buffer@l
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li r4,NUM_CACHE_LINES
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mtctr r4
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00: lwz r4,0(r3)
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addi r3,r3,L1_CACHE_BYTES /* Next line, please */
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bdnz 00b
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10: blr
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.previous
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