133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
/*
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* linux/arch/m68knommu/mm/memory.c
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*
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* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
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* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
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*
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* Based on:
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*
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* linux/arch/m68k/mm/memory.c
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/config.h>
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/io.h>
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/*
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* cache_clear() semantics: Clear any cache entries for the area in question,
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* without writing back dirty entries first. This is useful if the data will
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* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
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* _physical_ address.
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*/
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void cache_clear (unsigned long paddr, int len)
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{
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}
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/*
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* Define cache invalidate functions. The ColdFire 5407 is really
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* the only processor that needs to do some work here. Anything
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* that has separate data and instruction caches will be a problem.
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*/
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#ifdef CONFIG_M5407
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static __inline__ void cache_invalidate_lines(unsigned long paddr, int len)
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{
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unsigned long sset, eset;
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sset = (paddr & 0x00000ff0);
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eset = ((paddr + len) & 0x0000ff0) + 0x10;
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__asm__ __volatile__ (
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"nop\n\t"
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"clrl %%d0\n\t"
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"1:\n\t"
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"movel %0,%%a0\n\t"
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"addl %%d0,%%a0\n\t"
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"2:\n\t"
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".word 0xf4e8\n\t"
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"addl #0x10,%%a0\n\t"
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"cmpl %1,%%a0\n\t"
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"blt 2b\n\t"
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"addql #1,%%d0\n\t"
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"cmpil #4,%%d0\n\t"
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"bne 1b"
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: : "a" (sset), "a" (eset) : "d0", "a0" );
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}
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#else
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#define cache_invalidate_lines(a,b)
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#endif
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/*
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* cache_push() semantics: Write back any dirty cache data in the given area,
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* and invalidate the range in the instruction cache. It needs not (but may)
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* invalidate those entries also in the data cache. The range is defined by a
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* _physical_ address.
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*/
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void cache_push (unsigned long paddr, int len)
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{
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cache_invalidate_lines(paddr, len);
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}
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/*
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* cache_push_v() semantics: Write back any dirty cache data in the given
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* area, and invalidate those entries at least in the instruction cache. This
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* is intended to be used after data has been written that can be executed as
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* code later. The range is defined by a _user_mode_ _virtual_ address (or,
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* more exactly, the space is defined by the %sfc/%dfc register.)
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*/
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void cache_push_v (unsigned long vaddr, int len)
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{
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cache_invalidate_lines(vaddr, len);
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}
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/* Map some physical address range into the kernel address space. The
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* code is copied and adapted from map_chunk().
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*/
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unsigned long kernel_map(unsigned long paddr, unsigned long size,
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int nocacheflag, unsigned long *memavailp )
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{
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return paddr;
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}
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int is_in_rom(unsigned long addr)
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{
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extern unsigned long _ramstart, _ramend;
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/*
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* What we are really trying to do is determine if addr is
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* in an allocated kernel memory region. If not then assume
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* we cannot free it or otherwise de-allocate it. Ideally
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* we could restrict this to really being in a ROM or flash,
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* but that would need to be done on a board by board basis,
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* not globally.
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*/
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if ((addr < _ramstart) || (addr >= _ramend))
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return(1);
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/* Default case, not in ROM */
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return(0);
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}
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