200 lines
5.3 KiB
C
200 lines
5.3 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* arch/mips/ddb5xxx/ddb5477/irq.c
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* The irq setup and misc routines for DDB5476.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <asm/i8259.h>
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#include <asm/system.h>
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#include <asm/mipsregs.h>
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#include <asm/debug.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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/*
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* IRQ mapping
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*
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* 0-7: 8 CPU interrupts
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* 0 - software interrupt 0
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* 1 - software interrupt 1
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* 2 - most Vrc5477 interrupts are routed to this pin
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* 3 - (optional) some other interrupts routed to this pin for debugg
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* 4 - not used
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* 5 - not used
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* 6 - not used
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* 7 - cpu timer (used by default)
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*
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* 8-39: 32 Vrc5477 interrupt sources
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* (refer to the Vrc5477 manual)
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*/
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#define PCI0 DDB_INTPPES0
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#define PCI1 DDB_INTPPES1
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#define ACTIVE_LOW 1
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#define ACTIVE_HIGH 0
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#define LEVEL_SENSE 2
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#define EDGE_TRIGGER 0
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#define INTA 0
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#define INTB 1
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#define INTC 2
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#define INTD 3
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#define INTE 4
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static inline void
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set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
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{
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u32 reg_value;
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u32 reg_bitmask;
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reg_value = ddb_in32(pci);
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reg_bitmask = 0x3 << (intn * 2);
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reg_value &= ~reg_bitmask;
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reg_value |= (active | trigger) << (intn * 2);
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ddb_out32(pci, reg_value);
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}
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extern void vrc5477_irq_init(u32 base);
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extern void mips_cpu_irq_init(u32 base);
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extern asmlinkage void ddb5477_handle_int(void);
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
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void __init arch_init_irq(void)
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{
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/* by default, we disable all interrupts and route all vrc5477
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* interrupts to pin 0 (irq 2) */
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ddb_out32(DDB_INTCTRL0, 0);
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ddb_out32(DDB_INTCTRL1, 0);
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ddb_out32(DDB_INTCTRL2, 0);
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ddb_out32(DDB_INTCTRL3, 0);
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clear_c0_status(0xff00);
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set_c0_status(0x0400);
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/* setup PCI interrupt attributes */
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set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
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if (mips_machtype == MACH_NEC_ROCKHOPPERII)
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set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
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else
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set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
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/*
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* for debugging purpose, we enable several error interrupts
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* and route them to pin 1. (IP3)
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*/
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/* cpu parity check - 0 */
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ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
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/* cpu no-target decode - 1 */
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ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
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/* local bus read time-out - 7 */
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ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
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/* PCI SERR# - 14 */
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ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
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/* PCI internal error - 15 */
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ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
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/* IOPCI SERR# - 30 */
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ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
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/* IOPCI internal error - 31 */
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ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
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/* init all controllers */
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init_i8259_irqs();
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mips_cpu_irq_init(CPU_IRQ_BASE);
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vrc5477_irq_init(VRC5477_IRQ_BASE);
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/* setup cascade interrupts */
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setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
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setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
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/* hook up the first-level interrupt handler */
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set_except_vector(0, ddb5477_handle_int);
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}
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u8 i8259_interrupt_ack(void)
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{
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u8 irq;
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u32 reg;
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/* Set window 0 for interrupt acknowledge */
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reg = ddb_in32(DDB_PCIINIT10);
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ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
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irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
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ddb_out32(DDB_PCIINIT10, reg);
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/* i8259.c set the base vector to be 0x0 */
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return irq + I8259_IRQ_BASE;
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}
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/*
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* the first level int-handler will jump here if it is a vrc5477 irq
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*/
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#define NUM_5477_IRQS 32
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asmlinkage void
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vrc5477_irq_dispatch(struct pt_regs *regs)
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{
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u32 intStatus;
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u32 bitmask;
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u32 i;
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db_assert(ddb_in32(DDB_INT2STAT) == 0);
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db_assert(ddb_in32(DDB_INT3STAT) == 0);
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db_assert(ddb_in32(DDB_INT4STAT) == 0);
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db_assert(ddb_in32(DDB_NMISTAT) == 0);
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if (ddb_in32(DDB_INT1STAT) != 0) {
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#if defined(CONFIG_RUNTIME_DEBUG)
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vrc5477_show_int_regs();
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#endif
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panic("error interrupt has happened.");
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}
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intStatus = ddb_in32(DDB_INT0STAT);
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if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
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/* check for i8259 interrupts */
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if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
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int i8259_irq = i8259_interrupt_ack();
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do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
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return;
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}
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}
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for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
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/* do we need to "and" with the int mask? */
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if (intStatus & bitmask) {
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do_IRQ(VRC5477_IRQ_BASE + i, regs);
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return;
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}
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}
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}
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