original_kernel/drivers/clk/meson
Stephen Boyd 83907bf316 Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next
* clk-bindings:
  dt-bindings: clock: ti,cdce925: Convert to DT schema

* clk-renesas: (26 commits)
  clk: renesas: r8a779f0: Fix Ethernet Switch clocks
  clk: renesas: r8a779g0: Add Z0 clock support
  clk: renesas: r8a779g0: Add CMT clocks
  clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks
  clk: renesas: r8a779f0: Fix SCIF parent clocks
  clk: renesas: r8a779f0: Fix HSCIF parent clocks
  clk: renesas: r9a06g032: Repair grave increment error
  clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
  clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc
  clk: renesas: r8a779a0: Fix SD0H clock name
  clk: renesas: r8a779g0: Add RPC-IF clock
  clk: renesas: r8a779g0: Add SDHI clocks
  clk: renesas: r8a779f0: Add SASYNCPER internal clock
  clk: renesas: r8a779f0: Fix SD0H clock name
  clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
  clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
  clk: renesas: r8a779g0: Add TPU clock
  clk: renesas: r8a779g0: Add PWM clock
  clk: renesas: r8a779g0: Add SCIF clocks
  clk: renesas: r9a07g044: Add MTU3a clock and reset entry
  ...

* clk-amlogic:
  clk: meson: pll: add pcie lock retry workaround
  clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()

* clk-allwinner:
  clk: sunxi-ng: f1c100s: Add IR mod clock
  clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.h

* clk-ti:
  clk: ti: fix typo in ti_clk_retry_init() code comment
  clk: ti: dra7-atl: don't allocate `parent_names' variable
  clk: ti: change ti_clk_register[_omap_hw]() API
2022-12-12 11:12:52 -08:00
..
Kconfig
Makefile
axg-aoclk.c
axg-aoclk.h
axg-audio.c clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled() 2022-06-15 19:22:29 -07:00
axg-audio.h
axg.c
axg.h
clk-cpu-dyndiv.c
clk-cpu-dyndiv.h
clk-dualdiv.c
clk-dualdiv.h
clk-mpll.c
clk-mpll.h
clk-phase.c
clk-phase.h
clk-pll.c Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next 2022-12-12 11:12:52 -08:00
clk-pll.h
clk-regmap.c clk: meson: regmap: switch to determine_rate for the dividers 2021-06-30 11:37:02 -07:00
clk-regmap.h
g12a-aoclk.c
g12a-aoclk.h
g12a.c clk: meson: g12a: Add missing NNA source clocks for g12b 2021-06-09 21:39:50 +02:00
g12a.h
gxbb-aoclk.c
gxbb-aoclk.h
gxbb.c clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB 2021-11-30 10:28:52 +01:00
gxbb.h
meson-aoclk.c clk: meson: Hold reference returned by of_get_parent() 2022-08-19 14:29:00 -07:00
meson-aoclk.h
meson-eeclk.c clk: meson: Hold reference returned by of_get_parent() 2022-08-19 14:29:00 -07:00
meson-eeclk.h
meson8-ddr.c
meson8b.c clk: meson: Hold reference returned by of_get_parent() 2022-08-19 14:29:00 -07:00
meson8b.h clk: meson: meson8b: Initialize the HDMI PLL registers 2021-09-23 11:46:37 +02:00
parm.h
sclk-div.c
sclk-div.h
vid-pll-div.c
vid-pll-div.h