333 lines
7.1 KiB
C
333 lines
7.1 KiB
C
#ifndef __SPI_CAVIUM_H
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#define __SPI_CAVIUM_H
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#include <linux/clk.h>
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#define OCTEON_SPI_MAX_BYTES 9
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#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
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struct octeon_spi_regs {
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int config;
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int status;
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int tx;
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int data;
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};
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struct octeon_spi {
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void __iomem *register_base;
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u64 last_cfg;
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u64 cs_enax;
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int sys_freq;
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struct octeon_spi_regs regs;
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struct clk *clk;
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};
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#define OCTEON_SPI_CFG(x) (x->regs.config)
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#define OCTEON_SPI_STS(x) (x->regs.status)
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#define OCTEON_SPI_TX(x) (x->regs.tx)
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#define OCTEON_SPI_DAT0(x) (x->regs.data)
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int octeon_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg);
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/* MPI register descriptions */
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#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
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#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
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#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
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#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
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union cvmx_mpi_cfg {
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uint64_t u64;
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struct cvmx_mpi_cfg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t csena3:1;
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uint64_t csena2:1;
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uint64_t csena1:1;
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uint64_t csena0:1;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t csena:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t csena:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t csena0:1;
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uint64_t csena1:1;
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uint64_t csena2:1;
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uint64_t csena3:1;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} s;
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struct cvmx_mpi_cfg_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t reserved_12_15:4;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t csena:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t csena:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t reserved_12_15:4;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn30xx;
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struct cvmx_mpi_cfg_cn31xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t reserved_11_15:5;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t csena:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t csena:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t reserved_11_15:5;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn31xx;
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struct cvmx_mpi_cfg_cn30xx cn50xx;
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struct cvmx_mpi_cfg_cn61xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t reserved_14_15:2;
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uint64_t csena1:1;
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uint64_t csena0:1;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t reserved_6_6:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t reserved_6_6:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t csena0:1;
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uint64_t csena1:1;
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uint64_t reserved_14_15:2;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn61xx;
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struct cvmx_mpi_cfg_cn66xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t clkdiv:13;
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uint64_t csena3:1;
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uint64_t csena2:1;
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uint64_t reserved_12_13:2;
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uint64_t cslate:1;
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uint64_t tritx:1;
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uint64_t idleclks:2;
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uint64_t cshi:1;
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uint64_t reserved_6_6:1;
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uint64_t int_ena:1;
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uint64_t lsbfirst:1;
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uint64_t wireor:1;
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uint64_t clk_cont:1;
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uint64_t idlelo:1;
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uint64_t enable:1;
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#else
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uint64_t enable:1;
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uint64_t idlelo:1;
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uint64_t clk_cont:1;
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uint64_t wireor:1;
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uint64_t lsbfirst:1;
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uint64_t int_ena:1;
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uint64_t reserved_6_6:1;
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uint64_t cshi:1;
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uint64_t idleclks:2;
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uint64_t tritx:1;
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uint64_t cslate:1;
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uint64_t reserved_12_13:2;
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uint64_t csena2:1;
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uint64_t csena3:1;
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uint64_t clkdiv:13;
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uint64_t reserved_29_63:35;
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#endif
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} cn66xx;
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struct cvmx_mpi_cfg_cn61xx cnf71xx;
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};
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union cvmx_mpi_datx {
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uint64_t u64;
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struct cvmx_mpi_datx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_8_63:56;
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uint64_t data:8;
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#else
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uint64_t data:8;
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uint64_t reserved_8_63:56;
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#endif
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} s;
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struct cvmx_mpi_datx_s cn30xx;
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struct cvmx_mpi_datx_s cn31xx;
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struct cvmx_mpi_datx_s cn50xx;
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struct cvmx_mpi_datx_s cn61xx;
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struct cvmx_mpi_datx_s cn66xx;
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struct cvmx_mpi_datx_s cnf71xx;
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};
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union cvmx_mpi_sts {
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uint64_t u64;
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struct cvmx_mpi_sts_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_13_63:51;
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uint64_t rxnum:5;
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uint64_t reserved_1_7:7;
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uint64_t busy:1;
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#else
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uint64_t busy:1;
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uint64_t reserved_1_7:7;
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uint64_t rxnum:5;
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uint64_t reserved_13_63:51;
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#endif
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} s;
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struct cvmx_mpi_sts_s cn30xx;
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struct cvmx_mpi_sts_s cn31xx;
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struct cvmx_mpi_sts_s cn50xx;
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struct cvmx_mpi_sts_s cn61xx;
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struct cvmx_mpi_sts_s cn66xx;
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struct cvmx_mpi_sts_s cnf71xx;
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};
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union cvmx_mpi_tx {
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uint64_t u64;
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struct cvmx_mpi_tx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_22_63:42;
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uint64_t csid:2;
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uint64_t reserved_17_19:3;
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uint64_t leavecs:1;
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uint64_t reserved_13_15:3;
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uint64_t txnum:5;
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uint64_t reserved_5_7:3;
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uint64_t totnum:5;
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#else
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uint64_t totnum:5;
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uint64_t reserved_5_7:3;
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uint64_t txnum:5;
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uint64_t reserved_13_15:3;
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uint64_t leavecs:1;
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uint64_t reserved_17_19:3;
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uint64_t csid:2;
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uint64_t reserved_22_63:42;
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#endif
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} s;
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struct cvmx_mpi_tx_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_17_63:47;
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uint64_t leavecs:1;
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uint64_t reserved_13_15:3;
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uint64_t txnum:5;
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uint64_t reserved_5_7:3;
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uint64_t totnum:5;
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#else
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uint64_t totnum:5;
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uint64_t reserved_5_7:3;
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uint64_t txnum:5;
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uint64_t reserved_13_15:3;
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uint64_t leavecs:1;
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uint64_t reserved_17_63:47;
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#endif
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} cn30xx;
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struct cvmx_mpi_tx_cn30xx cn31xx;
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struct cvmx_mpi_tx_cn30xx cn50xx;
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struct cvmx_mpi_tx_cn61xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_21_63:43;
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uint64_t csid:1;
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uint64_t reserved_17_19:3;
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uint64_t leavecs:1;
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uint64_t reserved_13_15:3;
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uint64_t txnum:5;
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uint64_t reserved_5_7:3;
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uint64_t totnum:5;
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#else
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uint64_t totnum:5;
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uint64_t reserved_5_7:3;
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uint64_t txnum:5;
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uint64_t reserved_13_15:3;
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uint64_t leavecs:1;
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uint64_t reserved_17_19:3;
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uint64_t csid:1;
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uint64_t reserved_21_63:43;
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#endif
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} cn61xx;
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struct cvmx_mpi_tx_s cn66xx;
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struct cvmx_mpi_tx_cn61xx cnf71xx;
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};
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#endif /* __SPI_CAVIUM_H */
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