250 lines
6.4 KiB
C
250 lines
6.4 KiB
C
/*
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* Copyright 1999 - 2003 ARM Limited
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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#include <mach/cns3xxx.h>
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#include "core.h"
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static struct map_desc cns3xxx_io_desc[] __initdata = {
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{
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.virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_GPIOA_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_GPIOB_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_MISC_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = CNS3XXX_PM_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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void __init cns3xxx_map_io(void)
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{
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iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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}
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/* used by entry-macro.S */
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void __iomem *gic_cpu_base_addr;
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void __init cns3xxx_init_irq(void)
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{
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gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
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gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
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gic_cpu_init(0, gic_cpu_base_addr);
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}
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void cns3xxx_power_off(void)
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{
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u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
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u32 clkctrl;
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printk(KERN_INFO "powering system down...\n");
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clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
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clkctrl &= 0xfffff1ff;
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clkctrl |= (0x5 << 9); /* Hibernate */
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writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
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}
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/*
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* Timer
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*/
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static void __iomem *cns3xxx_tmr1;
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static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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int pclk = cns3xxx_cpu_clock() / 8;
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int reload;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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reload = pclk * 20 / (3 * HZ) * 0x25000;
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writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl |= (1 << 2) | (1 << 9);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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}
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static int cns3xxx_timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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return 0;
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}
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static struct clock_event_device cns3xxx_tmr1_clockevent = {
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.name = "cns3xxx timer1",
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.shift = 8,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = cns3xxx_timer_set_mode,
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.set_next_event = cns3xxx_timer_set_next_event,
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.rating = 350,
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.cpumask = cpu_all_mask,
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};
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static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
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{
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cns3xxx_tmr1_clockevent.irq = timer_irq;
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cns3xxx_tmr1_clockevent.mult =
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div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
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cns3xxx_tmr1_clockevent.shift);
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cns3xxx_tmr1_clockevent.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
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cns3xxx_tmr1_clockevent.min_delta_ns =
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clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
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clockevents_register_device(&cns3xxx_tmr1_clockevent);
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
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u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
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u32 val;
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/* Clear the interrupt */
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val = readl(stat);
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writel(val & ~(1 << 2), stat);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction cns3xxx_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = cns3xxx_timer_interrupt,
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};
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/*
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* Set up the clock source and clock events devices
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*/
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static void __init __cns3xxx_timer_init(unsigned int timer_irq)
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{
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u32 val;
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u32 irq_mask;
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/*
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* Initialise to a known state (all timers off)
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*/
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/* disable timer1 and timer2 */
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writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* stop free running timer3 */
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writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
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/* timer1 */
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writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
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writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
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/* mask irq, non-mask timer1 overflow */
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irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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irq_mask &= ~(1 << 2);
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irq_mask |= 0x03;
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writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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/* down counter */
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val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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val |= (1 << 9);
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writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* timer2 */
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writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
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writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
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/* mask irq */
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irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
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writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
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/* down counter */
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val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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val |= (1 << 10);
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writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
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/* Make irqs happen for the system timer */
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setup_irq(timer_irq, &cns3xxx_timer_irq);
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cns3xxx_clockevents_init(timer_irq);
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}
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static void __init cns3xxx_timer_init(void)
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{
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cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
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__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
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}
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struct sys_timer cns3xxx_timer = {
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.init = cns3xxx_timer_init,
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};
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