317 lines
7.8 KiB
C
317 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* motu-protocol-v3.c - a part of driver for MOTU FireWire series
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*
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* Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
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*/
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#include <linux/delay.h>
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#include "motu.h"
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#define V3_CLOCK_STATUS_OFFSET 0x0b14
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#define V3_FETCH_PCM_FRAMES 0x02000000
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#define V3_CLOCK_RATE_MASK 0x0000ff00
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#define V3_CLOCK_RATE_SHIFT 8
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#define V3_CLOCK_SOURCE_MASK 0x000000ff
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#define V3_OPT_IFACE_MODE_OFFSET 0x0c94
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#define V3_ENABLE_OPT_IN_IFACE_A 0x00000001
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#define V3_ENABLE_OPT_IN_IFACE_B 0x00000002
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#define V3_ENABLE_OPT_OUT_IFACE_A 0x00000100
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#define V3_ENABLE_OPT_OUT_IFACE_B 0x00000200
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#define V3_NO_ADAT_OPT_IN_IFACE_A 0x00010000
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#define V3_NO_ADAT_OPT_IN_IFACE_B 0x00100000
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#define V3_NO_ADAT_OPT_OUT_IFACE_A 0x00040000
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#define V3_NO_ADAT_OPT_OUT_IFACE_B 0x00400000
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static int v3_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data = (data & V3_CLOCK_RATE_MASK) >> V3_CLOCK_RATE_SHIFT;
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if (data >= ARRAY_SIZE(snd_motu_clock_rates))
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return -EIO;
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*rate = snd_motu_clock_rates[data];
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return 0;
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}
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static int v3_set_clock_rate(struct snd_motu *motu, unsigned int rate)
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{
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__be32 reg;
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u32 data;
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bool need_to_wait;
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int i, err;
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for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
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if (snd_motu_clock_rates[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(snd_motu_clock_rates))
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return -EINVAL;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~(V3_CLOCK_RATE_MASK | V3_FETCH_PCM_FRAMES);
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data |= i << V3_CLOCK_RATE_SHIFT;
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need_to_wait = data != be32_to_cpu(reg);
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reg = cpu_to_be32(data);
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err = snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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if (need_to_wait) {
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/* Cost expensive. */
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if (msleep_interruptible(4000) > 0)
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return -EINTR;
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}
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return 0;
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}
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static int v3_get_clock_source(struct snd_motu *motu,
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enum snd_motu_clock_source *src)
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{
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__be32 reg;
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u32 data;
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unsigned int val;
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int err;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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val = data & V3_CLOCK_SOURCE_MASK;
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if (val == 0x00) {
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*src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
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} else if (val == 0x01) {
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*src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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} else if (val == 0x02) {
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*src = SND_MOTU_CLOCK_SOURCE_SPH;
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} else if (val == 0x10) {
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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} else if (val == 0x18 || val == 0x19) {
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err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET,
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®, sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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if (val == 0x18) {
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if (data & V3_NO_ADAT_OPT_IN_IFACE_A)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_A;
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else
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_A;
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} else {
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if (data & V3_NO_ADAT_OPT_IN_IFACE_B)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_B;
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else
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_B;
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}
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} else {
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*src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
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}
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return 0;
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}
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static int v3_switch_fetching_mode(struct snd_motu *motu, bool enable)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return 0;
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data = be32_to_cpu(reg);
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if (enable)
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data |= V3_FETCH_PCM_FRAMES;
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else
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data &= ~V3_FETCH_PCM_FRAMES;
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static void calculate_fixed_part(struct snd_motu_packet_format *formats,
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enum amdtp_stream_direction dir,
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enum snd_motu_spec_flags flags,
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unsigned char analog_ports)
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{
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unsigned char pcm_chunks[3] = {0, 0, 0};
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formats->msg_chunks = 2;
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pcm_chunks[0] = analog_ports;
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pcm_chunks[1] = analog_ports;
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if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
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pcm_chunks[2] = analog_ports;
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if (dir == AMDTP_IN_STREAM) {
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if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
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pcm_chunks[2] += 2;
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}
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if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
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pcm_chunks[2] += 2;
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}
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if (flags & SND_MOTU_SPEC_TX_REVERB_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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} else {
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if (flags & SND_MOTU_SPEC_RX_SEPARATED_MAIN) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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// Packets to v3 units include 2 chunks for phone 1/2, except
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// for 176.4/192.0 kHz.
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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/*
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* At least, packets have two data chunks for S/PDIF on coaxial
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* interface.
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*/
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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/*
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* Fixed part consists of PCM chunks multiple of 4, with msg chunks. As
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* a result, this part can includes empty data chunks.
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*/
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formats->fixed_part_pcm_chunks[0] = round_up(2 + pcm_chunks[0], 4) - 2;
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formats->fixed_part_pcm_chunks[1] = round_up(2 + pcm_chunks[1], 4) - 2;
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if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
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formats->fixed_part_pcm_chunks[2] =
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round_up(2 + pcm_chunks[2], 4) - 2;
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}
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static void calculate_differed_part(struct snd_motu_packet_format *formats,
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enum snd_motu_spec_flags flags, u32 data,
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u32 a_enable_mask, u32 a_no_adat_mask,
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u32 b_enable_mask, u32 b_no_adat_mask)
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{
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unsigned char pcm_chunks[3] = {0, 0, 0};
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int i;
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if ((flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) && (data & a_enable_mask)) {
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if (data & a_no_adat_mask) {
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/*
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* Additional two data chunks for S/PDIF on optical
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* interface A. This includes empty data chunks.
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*/
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pcm_chunks[0] += 4;
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pcm_chunks[1] += 4;
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} else {
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/*
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* Additional data chunks for ADAT on optical interface
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* A.
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*/
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pcm_chunks[0] += 8;
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pcm_chunks[1] += 4;
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}
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}
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if ((flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) && (data & b_enable_mask)) {
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if (data & b_no_adat_mask) {
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/*
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* Additional two data chunks for S/PDIF on optical
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* interface B. This includes empty data chunks.
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*/
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pcm_chunks[0] += 4;
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pcm_chunks[1] += 4;
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} else {
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/*
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* Additional data chunks for ADAT on optical interface
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* B.
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*/
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pcm_chunks[0] += 8;
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pcm_chunks[1] += 4;
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}
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}
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for (i = 0; i < 3; ++i) {
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if (pcm_chunks[i] > 0)
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pcm_chunks[i] = round_up(pcm_chunks[i], 4);
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formats->differed_part_pcm_chunks[i] = pcm_chunks[i];
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}
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}
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static int v3_cache_packet_formats(struct snd_motu *motu)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM,
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motu->spec->flags, motu->spec->analog_in_ports);
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calculate_differed_part(&motu->tx_packet_formats,
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motu->spec->flags, data,
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V3_ENABLE_OPT_IN_IFACE_A, V3_NO_ADAT_OPT_IN_IFACE_A,
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V3_ENABLE_OPT_IN_IFACE_B, V3_NO_ADAT_OPT_IN_IFACE_B);
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calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM,
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motu->spec->flags, motu->spec->analog_out_ports);
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calculate_differed_part(&motu->rx_packet_formats,
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motu->spec->flags, data,
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V3_ENABLE_OPT_OUT_IFACE_A, V3_NO_ADAT_OPT_OUT_IFACE_A,
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V3_ENABLE_OPT_OUT_IFACE_B, V3_NO_ADAT_OPT_OUT_IFACE_B);
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motu->tx_packet_formats.pcm_byte_offset = 10;
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motu->rx_packet_formats.pcm_byte_offset = 10;
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return 0;
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}
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const struct snd_motu_protocol snd_motu_protocol_v3 = {
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.get_clock_rate = v3_get_clock_rate,
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.set_clock_rate = v3_set_clock_rate,
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.get_clock_source = v3_get_clock_source,
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.switch_fetching_mode = v3_switch_fetching_mode,
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.cache_packet_formats = v3_cache_packet_formats,
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};
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