315 lines
12 KiB
C
315 lines
12 KiB
C
/*
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* OMAP clock: data structure definitions, function prototypes, shared macros
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*
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* Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_OMAP_CLOCK_H
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#define __ARCH_ARM_OMAP_CLOCK_H
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#include <linux/list.h>
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struct module;
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struct clk;
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struct clockdomain;
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/**
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* struct clkops - some clock function pointers
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* @enable: fn ptr that enables the current clock in hardware
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* @disable: fn ptr that enables the current clock in hardware
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* @find_idlest: function returning the IDLEST register for the clock's IP blk
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* @find_companion: function returning the "companion" clk reg for the clock
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* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
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* @deny_idle: fn ptr that disables autoidle for the current clock in hardware
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*
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* A "companion" clk is an accompanying clock to the one being queried
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* that must be enabled for the IP module connected to the clock to
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* become accessible by the hardware. Neither @find_idlest nor
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* @find_companion should be needed; that information is IP
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* block-specific; the hwmod code has been created to handle this, but
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* until hwmod data is ready and drivers have been converted to use PM
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* runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
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* @find_companion must, unfortunately, remain.
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*/
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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void (*find_idlest)(struct clk *, void __iomem **,
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u8 *, u8 *);
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void (*find_companion)(struct clk *, void __iomem **,
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u8 *);
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void (*allow_idle)(struct clk *);
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void (*deny_idle)(struct clk *);
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};
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#ifdef CONFIG_ARCH_OMAP2PLUS
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/* struct clksel_rate.flags possibilities */
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#define RATE_IN_242X (1 << 0)
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#define RATE_IN_243X (1 << 1)
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#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
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#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
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#define RATE_IN_36XX (1 << 4)
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#define RATE_IN_4430 (1 << 5)
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#define RATE_IN_TI816X (1 << 6)
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#define RATE_IN_4460 (1 << 7)
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
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#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
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#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
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/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
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#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
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/**
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* struct clksel_rate - register bitfield values corresponding to clk divisors
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* @val: register bitfield value (shifted to bit 0)
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* @div: clock divisor corresponding to @val
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* @flags: (see "struct clksel_rate.flags possibilities" above)
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*
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* @val should match the value of a read from struct clk.clksel_reg
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* AND'ed with struct clk.clksel_mask, shifted right to bit 0.
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*
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* @div is the divisor that should be applied to the parent clock's rate
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* to produce the current clock's rate.
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*/
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struct clksel_rate {
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u32 val;
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u8 div;
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u8 flags;
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};
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/**
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* struct clksel - available parent clocks, and a pointer to their divisors
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* @parent: struct clk * to a possible parent clock
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* @rates: available divisors for this parent clock
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*
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* A struct clksel is always associated with one or more struct clks
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* and one or more struct clksel_rates.
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*/
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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/**
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* struct dpll_data - DPLL registers and integration data
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* @mult_div1_reg: register containing the DPLL M and N bitfields
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* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
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* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
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* @clk_bypass: struct clk pointer to the clock's bypass clock input
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* @clk_ref: struct clk pointer to the clock's reference clock input
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* @control_reg: register containing the DPLL mode bitfield
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
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* @max_multiplier: maximum valid non-bypass multiplier value (actual)
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* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
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* @min_divider: minimum valid non-bypass divider value (actual)
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* @max_divider: maximum valid non-bypass divider value (actual)
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* @modes: possible values of @enable_mask
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* @autoidle_reg: register containing the DPLL autoidle mode bitfield
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* @idlest_reg: register containing the DPLL idle status bitfield
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* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
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* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
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* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
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* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
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* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
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* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
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* @flags: DPLL type/features (see below)
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*
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* Possible values for @flags:
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* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
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*
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* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
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*
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically
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* correct to only have one @clk_bypass pointer.
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*
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
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* @last_rounded_n) should be separated from the runtime-fixed fields
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* and placed into a different structure, so that the runtime-fixed data
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* can be placed into read-only space.
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*/
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struct dpll_data {
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void __iomem *mult_div1_reg;
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u32 mult_mask;
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u32 div1_mask;
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struct clk *clk_bypass;
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struct clk *clk_ref;
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void __iomem *control_reg;
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u32 enable_mask;
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unsigned long last_rounded_rate;
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u16 last_rounded_m;
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u16 max_multiplier;
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u8 last_rounded_n;
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u8 min_divider;
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u16 max_divider;
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u8 modes;
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
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void __iomem *autoidle_reg;
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void __iomem *idlest_reg;
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u32 autoidle_mask;
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u32 freqsel_mask;
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u32 idlest_mask;
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u32 dco_mask;
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u32 sddiv_mask;
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u8 auto_recal_bit;
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u8 recal_en_bit;
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u8 recal_st_bit;
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# endif
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u8 flags;
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};
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#endif
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/*
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* struct clk.flags possibilities
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*
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* XXX document the rest of the clock flags here
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*
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* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
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* bits share the same register. This flag allows the
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* omap4_dpllmx*() code to determine which GATE_CTRL bit field
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* should be used. This is a temporary solution - a better approach
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* would be to associate clock type-specific data with the clock,
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* similar to the struct dpll_data approach.
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*/
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
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#define CLOCK_IDLE_CONTROL (1 << 1)
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#define CLOCK_NO_IDLE_PARENT (1 << 2)
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#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
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#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
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#define CLOCK_CLKOUTX2 (1 << 5)
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/**
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* struct clk - OMAP struct clk
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* @node: list_head connecting this clock into the full clock list
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* @ops: struct clkops * for this clock
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* @name: the name of the clock in the hardware (used in hwmod data and debug)
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* @parent: pointer to this clock's parent struct clk
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* @children: list_head connecting to the child clks' @sibling list_heads
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* @sibling: list_head connecting this clk to its parent clk's @children
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* @rate: current clock rate
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* @enable_reg: register to write to enable the clock (see @enable_bit)
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* @recalc: fn ptr that returns the clock's current rate
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* @set_rate: fn ptr that can change the clock's current rate
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* @round_rate: fn ptr that can round the clock's current rate
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* @init: fn ptr to do clock-specific initialization
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
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* @usecount: number of users that have requested this clock to be enabled
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* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
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* @flags: see "struct clk.flags possibilities" above
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* @clksel_reg: for clksel clks, register va containing src/divisor select
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* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
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* @clksel: for clksel clks, pointer to struct clksel for this clock
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* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
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* @clkdm_name: clockdomain name that this clock is contained in
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* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
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* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
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* @src_offset: bitshift for source selection bitfield (OMAP1 only)
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*
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* XXX @rate_offset, @src_offset should probably be removed and OMAP1
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* clock code converted to use clksel.
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*
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* XXX @usecount is poorly named. It should be "enable_count" or
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* something similar. "users" in the description refers to kernel
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* code (core code or drivers) that have called clk_enable() and not
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* yet called clk_disable(); the usecount of parent clocks is also
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* incremented by the clock code when clk_enable() is called on child
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* clocks and decremented by the clock code when clk_disable() is
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* called on child clocks.
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*
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* XXX @clkdm, @usecount, @children, @sibling should be marked for
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* internal use only.
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*
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* @children and @sibling are used to optimize parent-to-child clock
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* tree traversals. (child-to-parent traversals use @parent.)
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*
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* XXX The notion of the clock's current rate probably needs to be
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* separated from the clock's target rate.
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*/
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struct clk {
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struct list_head node;
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const struct clkops *ops;
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const char *name;
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struct clk *parent;
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struct list_head children;
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struct list_head sibling; /* node for children */
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unsigned long rate;
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void __iomem *enable_reg;
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unsigned long (*recalc)(struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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u8 enable_bit;
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s8 usecount;
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u8 fixed_div;
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u8 flags;
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#ifdef CONFIG_ARCH_OMAP2PLUS
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void __iomem *clksel_reg;
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u32 clksel_mask;
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const struct clksel *clksel;
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struct dpll_data *dpll_data;
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const char *clkdm_name;
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struct clockdomain *clkdm;
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#else
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u8 rate_offset;
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u8 src_offset;
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#endif
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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struct dentry *dent; /* For visible tree hierarchy */
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#endif
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};
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struct cpufreq_frequency_table;
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struct clk_functions {
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int (*clk_enable)(struct clk *clk);
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void (*clk_disable)(struct clk *clk);
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long (*clk_round_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_parent)(struct clk *clk, struct clk *parent);
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void (*clk_allow_idle)(struct clk *clk);
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void (*clk_deny_idle)(struct clk *clk);
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void (*clk_disable_unused)(struct clk *clk);
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#ifdef CONFIG_CPU_FREQ
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void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
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void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
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#endif
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};
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extern int mpurate;
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extern int clk_init(struct clk_functions *custom_clocks);
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extern void clk_preinit(struct clk *clk);
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extern int clk_register(struct clk *clk);
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extern void clk_reparent(struct clk *child, struct clk *parent);
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extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern void recalculate_root_clocks(void);
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extern unsigned long followparent_recalc(struct clk *clk);
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extern void clk_enable_init_clocks(void);
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unsigned long omap_fixed_divisor_recalc(struct clk *clk);
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#ifdef CONFIG_CPU_FREQ
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extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
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extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
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#endif
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extern struct clk *omap_clk_get_by_name(const char *name);
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extern int omap_clk_enable_autoidle_all(void);
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extern int omap_clk_disable_autoidle_all(void);
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extern const struct clkops clkops_null;
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extern struct clk dummy_ck;
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#endif
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