125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_GPU_H__
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#define __MSM_GPU_H__
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "msm_drv.h"
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#include "msm_ringbuffer.h"
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struct msm_gem_submit;
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/* So far, with hardware that I've seen to date, we can have:
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* + zero, one, or two z180 2d cores
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* + a3xx or a2xx 3d core, which share a common CP (the firmware
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* for the CP seems to implement some different PM4 packet types
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* but the basics of cmdstream submission are the same)
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*
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* Which means that the eventual complete "class" hierarchy, once
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* support for all past and present hw is in place, becomes:
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* + msm_gpu
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* + adreno_gpu
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* + a3xx_gpu
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* + a2xx_gpu
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* + z180_gpu
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*/
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struct msm_gpu_funcs {
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int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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int (*hw_init)(struct msm_gpu *gpu);
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int (*pm_suspend)(struct msm_gpu *gpu);
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int (*pm_resume)(struct msm_gpu *gpu);
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int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx);
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void (*flush)(struct msm_gpu *gpu);
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void (*idle)(struct msm_gpu *gpu);
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irqreturn_t (*irq)(struct msm_gpu *irq);
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uint32_t (*last_fence)(struct msm_gpu *gpu);
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void (*recover)(struct msm_gpu *gpu);
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void (*destroy)(struct msm_gpu *gpu);
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#ifdef CONFIG_DEBUG_FS
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/* show GPU status in debugfs: */
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void (*show)(struct msm_gpu *gpu, struct seq_file *m);
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#endif
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};
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struct msm_gpu {
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const char *name;
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struct drm_device *dev;
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const struct msm_gpu_funcs *funcs;
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struct msm_ringbuffer *rb;
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uint32_t rb_iova;
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/* list of GEM active objects: */
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struct list_head active_list;
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uint32_t submitted_fence;
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/* worker for handling active-list retiring: */
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struct work_struct retire_work;
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void __iomem *mmio;
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int irq;
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struct iommu_domain *iommu;
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int id;
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/* Power Control: */
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struct regulator *gpu_reg, *gpu_cx;
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struct clk *ebi1_clk, *grp_clks[5];
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uint32_t fast_rate, slow_rate, bus_freq;
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uint32_t bsc;
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/* Hang Detction: */
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#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
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#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
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struct timer_list hangcheck_timer;
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uint32_t hangcheck_fence;
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struct work_struct recover_work;
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};
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static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
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{
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msm_writel(data, gpu->mmio + (reg << 2));
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}
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static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
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{
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return msm_readl(gpu->mmio + (reg << 2));
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}
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int msm_gpu_pm_suspend(struct msm_gpu *gpu);
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int msm_gpu_pm_resume(struct msm_gpu *gpu);
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void msm_gpu_retire(struct msm_gpu *gpu);
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int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx);
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int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
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const char *name, const char *ioname, const char *irqname, int ringsz);
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void msm_gpu_cleanup(struct msm_gpu *gpu);
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struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
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void __init a3xx_register(void);
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void __exit a3xx_unregister(void);
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#endif /* __MSM_GPU_H__ */
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