292 lines
6.4 KiB
C
292 lines
6.4 KiB
C
/*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2013 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "core.h"
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/* Sysctrl registers in Hi3620 SoC */
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#define SCISOEN 0xc0
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#define SCISODIS 0xc4
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#define SCPERPWREN 0xd0
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#define SCPERPWRDIS 0xd4
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#define SCCPUCOREEN 0xf4
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#define SCCPUCOREDIS 0xf8
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#define SCPERCTRL0 0x200
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#define SCCPURSTEN 0x410
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#define SCCPURSTDIS 0x414
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/*
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* bit definition in SCISOEN/SCPERPWREN/...
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*
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* CPU2_ISO_CTRL (1 << 5)
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* CPU3_ISO_CTRL (1 << 6)
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* ...
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*/
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#define CPU2_ISO_CTRL (1 << 5)
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/*
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* bit definition in SCPERCTRL0
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*
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* CPU0_WFI_MASK_CFG (1 << 28)
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* CPU1_WFI_MASK_CFG (1 << 29)
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* ...
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*/
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#define CPU0_WFI_MASK_CFG (1 << 28)
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/*
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* bit definition in SCCPURSTEN/...
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*
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* CPU0_SRST_REQ_EN (1 << 0)
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* CPU1_SRST_REQ_EN (1 << 1)
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* ...
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*/
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#define CPU0_HPM_SRST_REQ_EN (1 << 22)
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#define CPU0_DBG_SRST_REQ_EN (1 << 12)
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#define CPU0_NEON_SRST_REQ_EN (1 << 4)
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#define CPU0_SRST_REQ_EN (1 << 0)
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#define HIX5HD2_PERI_CRG20 0x50
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#define CRG20_CPU1_RESET (1 << 17)
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#define HIX5HD2_PERI_PMC0 0x1000
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#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
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#define PMC0_CPU1_PMC_ENABLE (1 << 7)
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#define PMC0_CPU1_POWERDOWN (1 << 3)
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#define HIP01_PERI9 0x50
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#define PERI9_CPU1_RESET (1 << 1)
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enum {
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HI3620_CTRL,
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ERROR_CTRL,
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};
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static void __iomem *ctrl_base;
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static int id;
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static void set_cpu_hi3620(int cpu, bool enable)
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{
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u32 val = 0;
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if (enable) {
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/* MTCMOS set */
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if ((cpu == 2) || (cpu == 3))
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writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
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ctrl_base + SCPERPWREN);
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udelay(100);
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/* Enable core */
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writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
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/* unreset */
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val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
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| CPU0_SRST_REQ_EN;
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writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
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/* reset */
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val |= CPU0_HPM_SRST_REQ_EN;
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writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
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/* ISO disable */
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if ((cpu == 2) || (cpu == 3))
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writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
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ctrl_base + SCISODIS);
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udelay(1);
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/* WFI Mask */
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val = readl_relaxed(ctrl_base + SCPERCTRL0);
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val &= ~(CPU0_WFI_MASK_CFG << cpu);
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writel_relaxed(val, ctrl_base + SCPERCTRL0);
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/* Unreset */
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val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
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| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
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writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
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} else {
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/* wfi mask */
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val = readl_relaxed(ctrl_base + SCPERCTRL0);
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val |= (CPU0_WFI_MASK_CFG << cpu);
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writel_relaxed(val, ctrl_base + SCPERCTRL0);
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/* disable core*/
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writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
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if ((cpu == 2) || (cpu == 3)) {
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/* iso enable */
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writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
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ctrl_base + SCISOEN);
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udelay(1);
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}
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/* reset */
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val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
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| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
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writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
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if ((cpu == 2) || (cpu == 3)) {
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/* MTCMOS unset */
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writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
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ctrl_base + SCPERPWRDIS);
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udelay(100);
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}
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}
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}
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static int hi3xxx_hotplug_init(void)
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{
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struct device_node *node;
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node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
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if (node) {
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ctrl_base = of_iomap(node, 0);
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id = HI3620_CTRL;
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return 0;
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}
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id = ERROR_CTRL;
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return -ENOENT;
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}
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void hi3xxx_set_cpu(int cpu, bool enable)
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{
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if (!ctrl_base) {
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if (hi3xxx_hotplug_init() < 0)
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return;
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}
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if (id == HI3620_CTRL)
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set_cpu_hi3620(cpu, enable);
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}
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static bool hix5hd2_hotplug_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
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if (np) {
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ctrl_base = of_iomap(np, 0);
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return true;
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}
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return false;
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}
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void hix5hd2_set_cpu(int cpu, bool enable)
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{
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u32 val = 0;
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if (!ctrl_base)
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if (!hix5hd2_hotplug_init())
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BUG();
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if (enable) {
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/* power on cpu1 */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
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val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
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val |= PMC0_CPU1_PMC_ENABLE;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
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/* unreset */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
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val &= ~CRG20_CPU1_RESET;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
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} else {
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/* power down cpu1 */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
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val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
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val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
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/* reset */
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val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
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val |= CRG20_CPU1_RESET;
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writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
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}
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}
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void hip01_set_cpu(int cpu, bool enable)
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{
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unsigned int temp;
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struct device_node *np;
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if (!ctrl_base) {
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np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
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if (np)
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ctrl_base = of_iomap(np, 0);
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else
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BUG();
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}
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if (enable) {
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/* reset on CPU1 */
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temp = readl_relaxed(ctrl_base + HIP01_PERI9);
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temp |= PERI9_CPU1_RESET;
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writel_relaxed(temp, ctrl_base + HIP01_PERI9);
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udelay(50);
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/* unreset on CPU1 */
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temp = readl_relaxed(ctrl_base + HIP01_PERI9);
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temp &= ~PERI9_CPU1_RESET;
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writel_relaxed(temp, ctrl_base + HIP01_PERI9);
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}
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}
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static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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flush_cache_all();
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/*
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* Turn off coherency and L1 D-cache
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*/
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asm volatile(
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, #0x40\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, #0x04\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "r" (0)
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: "cc");
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void hi3xxx_cpu_die(unsigned int cpu)
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{
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cpu_enter_lowpower();
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hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
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cpu_do_idle();
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/* We should have never returned from idle */
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panic("cpu %d unexpectedly exit from shutdown\n", cpu);
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}
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int hi3xxx_cpu_kill(unsigned int cpu)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(50);
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while (hi3xxx_get_cpu_jump(cpu))
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if (time_after(jiffies, timeout))
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return 0;
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hi3xxx_set_cpu(cpu, false);
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return 1;
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}
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void hix5hd2_cpu_die(unsigned int cpu)
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{
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flush_cache_all();
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hix5hd2_set_cpu(cpu, false);
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}
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#endif
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