371 lines
9.4 KiB
C
371 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef _ASM_ARC_ARCREGS_H
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#define _ASM_ARC_ARCREGS_H
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/* Build Configuration Registers */
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#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
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#define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
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#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
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#define ARC_REG_CRC_BCR 0x62
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#define ARC_REG_VECBASE_BCR 0x68
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#define ARC_REG_PERIBASE_BCR 0x69
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#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
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#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
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#define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
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#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
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#define ARC_REG_SLC_BCR 0xce
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#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
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#define ARC_REG_AP_BCR 0x76
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#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
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#define ARC_REG_XY_MEM_BCR 0x79
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#define ARC_REG_MAC_BCR 0x7a
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#define ARC_REG_MPY_BCR 0x7b
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#define ARC_REG_SWAP_BCR 0x7c
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#define ARC_REG_NORM_BCR 0x7d
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#define ARC_REG_MIXMAX_BCR 0x7e
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#define ARC_REG_BARREL_BCR 0x7f
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#define ARC_REG_D_UNCACH_BCR 0x6A
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#define ARC_REG_BPU_BCR 0xc0
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#define ARC_REG_ISA_CFG_BCR 0xc1
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#define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
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#define ARC_REG_RTT_BCR 0xF2
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#define ARC_REG_IRQ_BCR 0xF3
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#define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
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#define ARC_REG_SMART_BCR 0xFF
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#define ARC_REG_CLUSTER_BCR 0xcf
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#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
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#define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
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#define ARC_REG_FPU_CTRL 0x300
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#define ARC_REG_FPU_STATUS 0x301
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/* Common for ARCompact and ARCv2 status register */
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#define ARC_REG_STATUS32 0x0A
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/* status32 Bits Positions */
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#define STATUS_AE_BIT 5 /* Exception active */
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#define STATUS_DE_BIT 6 /* PC is in delay slot */
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#define STATUS_U_BIT 7 /* User/Kernel mode */
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#define STATUS_Z_BIT 11
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#define STATUS_L_BIT 12 /* Loop inhibit */
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/* These masks correspond to the status word(STATUS_32) bits */
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#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
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#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
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#define STATUS_U_MASK (1<<STATUS_U_BIT)
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#define STATUS_Z_MASK (1<<STATUS_Z_BIT)
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#define STATUS_L_MASK (1<<STATUS_L_BIT)
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/*
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* ECR: Exception Cause Reg bits-n-pieces
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* [23:16] = Exception Vector
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* [15: 8] = Exception Cause Code
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* [ 7: 0] = Exception Parameters (for certain types only)
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*/
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#ifdef CONFIG_ISA_ARCOMPACT
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#define ECR_V_MEM_ERR 0x01
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#define ECR_V_INSN_ERR 0x02
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#define ECR_V_MACH_CHK 0x20
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#define ECR_V_ITLB_MISS 0x21
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#define ECR_V_DTLB_MISS 0x22
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#define ECR_V_PROTV 0x23
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#define ECR_V_TRAP 0x25
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#else
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#define ECR_V_MEM_ERR 0x01
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#define ECR_V_INSN_ERR 0x02
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#define ECR_V_MACH_CHK 0x03
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#define ECR_V_ITLB_MISS 0x04
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#define ECR_V_DTLB_MISS 0x05
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#define ECR_V_PROTV 0x06
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#define ECR_V_TRAP 0x09
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#define ECR_V_MISALIGN 0x0d
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#endif
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/* DTLB Miss and Protection Violation Cause Codes */
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#define ECR_C_PROTV_INST_FETCH 0x00
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#define ECR_C_PROTV_LOAD 0x01
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#define ECR_C_PROTV_STORE 0x02
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#define ECR_C_PROTV_XCHG 0x03
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#define ECR_C_PROTV_MISALIG_DATA 0x04
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#define ECR_C_BIT_PROTV_MISALIG_DATA 10
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/* Machine Check Cause Code Values */
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#define ECR_C_MCHK_DUP_TLB 0x01
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/* DTLB Miss Exception Cause Code Values */
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#define ECR_C_BIT_DTLB_LD_MISS 8
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#define ECR_C_BIT_DTLB_ST_MISS 9
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/* Auxiliary registers */
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#define AUX_IDENTITY 4
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#define AUX_EXEC_CTRL 8
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#define AUX_INTR_VEC_BASE 0x25
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#define AUX_VOL 0x5e
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/*
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* Floating Pt Registers
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* Status regs are read-only (build-time) so need not be saved/restored
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*/
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#define ARC_AUX_FP_STAT 0x300
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#define ARC_AUX_DPFP_1L 0x301
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#define ARC_AUX_DPFP_1H 0x302
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#define ARC_AUX_DPFP_2L 0x303
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#define ARC_AUX_DPFP_2H 0x304
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#define ARC_AUX_DPFP_STAT 0x305
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/*
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* DSP-related registers
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* Registers names must correspond to dsp_callee_regs structure fields names
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* for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
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*/
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#define ARC_AUX_DSP_BUILD 0x7A
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#define ARC_AUX_ACC0_LO 0x580
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#define ARC_AUX_ACC0_GLO 0x581
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#define ARC_AUX_ACC0_HI 0x582
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#define ARC_AUX_ACC0_GHI 0x583
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#define ARC_AUX_DSP_BFLY0 0x598
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#define ARC_AUX_DSP_CTRL 0x59F
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#define ARC_AUX_DSP_FFT_CTRL 0x59E
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#define ARC_AUX_AGU_BUILD 0xCC
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#define ARC_AUX_AGU_AP0 0x5C0
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#define ARC_AUX_AGU_AP1 0x5C1
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#define ARC_AUX_AGU_AP2 0x5C2
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#define ARC_AUX_AGU_AP3 0x5C3
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#define ARC_AUX_AGU_OS0 0x5D0
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#define ARC_AUX_AGU_OS1 0x5D1
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#define ARC_AUX_AGU_MOD0 0x5E0
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#define ARC_AUX_AGU_MOD1 0x5E1
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#define ARC_AUX_AGU_MOD2 0x5E2
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#define ARC_AUX_AGU_MOD3 0x5E3
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#ifndef __ASSEMBLY__
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#include <soc/arc/aux.h>
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/* Helpers */
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#define TO_KB(bytes) ((bytes) >> 10)
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#define TO_MB(bytes) (TO_KB(bytes) >> 10)
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#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
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#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
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/*
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***************************************************************
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* Build Configuration Registers, with encoded hardware config
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*/
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struct bcr_identity {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int chip_id:16, cpu_id:8, family:8;
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#else
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unsigned int family:8, cpu_id:8, chip_id:16;
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#endif
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};
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struct bcr_isa_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
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pad1:12, ver:8;
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#else
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unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
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ldd:1, pad2:4, div_rem:4;
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#endif
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};
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struct bcr_uarch_build {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, prod:8, maj:8, min:8;
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#else
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unsigned int min:8, maj:8, prod:8, pad:8;
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#endif
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};
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struct bcr_mmu_3 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
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u_itlb:4, u_dtlb:4;
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#else
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unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
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ways:4, ver:8;
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#endif
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};
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struct bcr_mmu_4 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
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n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
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#else
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/* DTLB ITLB JES JE JA */
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unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
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pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
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#endif
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};
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struct bcr_cache {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
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#else
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unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
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#endif
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};
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struct bcr_slc_cfg {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:24, way:2, lsz:2, sz:4;
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#else
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unsigned int sz:4, lsz:2, way:2, pad:24;
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#endif
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};
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struct bcr_clust_cfg {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
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#else
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unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
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#endif
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};
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struct bcr_volatile {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int start:4, limit:4, pad:22, order:1, disable:1;
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#else
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unsigned int disable:1, order:1, pad:22, limit:4, start:4;
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#endif
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};
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struct bcr_mpy {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
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#else
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unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
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#endif
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};
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struct bcr_iccm_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int base:16, pad:5, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, pad:5, base:16;
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#endif
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};
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struct bcr_iccm_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
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#else
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unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
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#endif
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};
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struct bcr_dccm_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res:21, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, res:21;
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#endif
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};
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struct bcr_dccm_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
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#else
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unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
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#endif
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};
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/* ARCompact: Both SP and DP FPU BCRs have same format */
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struct bcr_fp_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int fast:1, ver:8;
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#else
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unsigned int ver:8, fast:1;
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#endif
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};
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struct bcr_fp_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
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#else
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unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
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#endif
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};
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struct bcr_actionpoint {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:21, min:1, num:2, ver:8;
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#else
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unsigned int ver:8, num:2, min:1, pad:21;
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#endif
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};
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#include <soc/arc/timers.h>
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struct bcr_bpu_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
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#else
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unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
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#endif
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};
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struct bcr_bpu_arcv2 {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
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#else
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unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
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#endif
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};
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/* Error Protection Build: ECC/Parity */
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struct bcr_erp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
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#else
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unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
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#endif
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};
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/* Error Protection Control */
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struct ctl_erp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
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#else
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unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
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#endif
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};
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struct bcr_lpb {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:16, entries:8, ver:8;
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#else
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unsigned int ver:8, entries:8, pad:16;
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#endif
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};
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struct bcr_generic {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int info:24, ver:8;
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#else
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unsigned int ver:8, info:24;
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#endif
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};
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static inline int is_isa_arcv2(void)
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{
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return IS_ENABLED(CONFIG_ISA_ARCV2);
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}
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static inline int is_isa_arcompact(void)
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{
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return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
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}
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#endif /* __ASEMBLY__ */
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#endif /* _ASM_ARC_ARCREGS_H */
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