300 lines
9.6 KiB
Plaintext
300 lines
9.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G3S SoC
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a08g045-cpg.h>
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/ {
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compatible = "renesas,r9a08g045";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0>;
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device_type = "cpu";
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#cooling-cells = <2>;
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
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};
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L3_CA55: cache-controller-0 {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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cache-size = <0x40000>;
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};
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};
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extal_clk: extal-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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scif0: serial@1004b800 {
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compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
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reg = <0 0x1004b800 0 0x400>;
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interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
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status = "disabled";
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};
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a08g045-cpg";
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reg = <0 0x11010000 0 0x10000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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sysc: system-controller@11020000 {
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compatible = "renesas,r9a08g045-sysc";
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reg = <0 0x11020000 0 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "lpm_int", "ca55stbydone_int",
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"cm33stbyr_int", "ca55_deny";
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status = "disabled";
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};
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pinctrl: pinctrl@11030000 {
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compatible = "renesas,r9a08g045-pinctrl";
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reg = <0 0x11030000 0 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&irqc>;
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gpio-ranges = <&pinctrl 0 0 152>;
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clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A08G045_GPIO_RSTN>,
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<&cpg R9A08G045_GPIO_PORT_RESETN>,
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<&cpg R9A08G045_GPIO_SPARE_RESETN>;
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};
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irqc: interrupt-controller@11050000 {
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compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x11050000 0 0x10000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "nmi",
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"irq0", "irq1", "irq2", "irq3",
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"irq4", "irq5", "irq6", "irq7",
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"tint0", "tint1", "tint2", "tint3",
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"tint4", "tint5", "tint6", "tint7",
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"tint8", "tint9", "tint10", "tint11",
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"tint12", "tint13", "tint14", "tint15",
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"tint16", "tint17", "tint18", "tint19",
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"tint20", "tint21", "tint22", "tint23",
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"tint24", "tint25", "tint26", "tint27",
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"tint28", "tint29", "tint30", "tint31",
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"bus-err", "ec7tie1-0", "ec7tie2-0",
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"ec7tiovf-0";
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clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
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<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
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clock-names = "clk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A08G045_IA55_RESETN>;
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};
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sdhi0: mmc@11c00000 {
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compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
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reg = <0x0 0x11c00000 0 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
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<&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
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<&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
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<&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
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clock-names = "core", "clkh", "cd", "aclk";
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resets = <&cpg R9A08G045_SDHI0_IXRST>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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sdhi1: mmc@11c10000 {
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compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
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reg = <0x0 0x11c10000 0 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
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<&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
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<&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
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<&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
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clock-names = "core", "clkh", "cd", "aclk";
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resets = <&cpg R9A08G045_SDHI1_IXRST>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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sdhi2: mmc@11c20000 {
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compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
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reg = <0x0 0x11c20000 0 0x10000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
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<&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
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<&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
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<&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
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clock-names = "core", "clkh", "cd", "aclk";
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resets = <&cpg R9A08G045_SDHI2_IXRST>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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eth0: ethernet@11c30000 {
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compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
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reg = <0 0x11c30000 0 0x10000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mux", "fil", "arp_ns";
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phy-mode = "rgmii";
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clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
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<&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
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<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
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clock-names = "axi", "chi", "refclk";
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resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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eth1: ethernet@11c40000 {
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compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
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reg = <0 0x11c40000 0 0x10000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mux", "fil", "arp_ns";
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phy-mode = "rgmii";
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clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
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<&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
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<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
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clock-names = "axi", "chi", "refclk";
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resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gic: interrupt-controller@12400000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x12400000 0 0x40000>,
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<0x0 0x12440000 0 0x60000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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wdt0: watchdog@12800800 {
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compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
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reg = <0 0x12800800 0 0x400>;
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clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
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<&cpg CPG_MOD R9A08G045_WDT0_CLK>;
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clock-names = "pclk", "oscclk";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "wdt", "perrout";
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resets = <&cpg R9A08G045_WDT0_PRESETN>;
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power-domains = <&cpg>;
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status = "disabled";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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