266 lines
6.0 KiB
Plaintext
266 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2UL SMARC SOM common parts
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/ {
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aliases {
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ethernet0 = ð0;
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ethernet1 = ð1;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x38000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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#if !(SW_SW0_DEV_SEL)
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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states = <3300000 1>, <1800000 0>;
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regulator-boot-on;
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gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
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regulator-always-on;
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};
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#endif
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};
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#if (SW_SW0_DEV_SEL)
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&adc {
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pinctrl-0 = <&adc_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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#endif
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#if (!SW_ET0_EN_N)
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ð0 {
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pinctrl-0 = <ð0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy0: ethernet-phy@7 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupt-parent = <&irqc>;
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interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
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rxc-skew-psec = <2400>;
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txc-skew-psec = <2400>;
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rxdv-skew-psec = <0>;
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txen-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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#endif
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ð1 {
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pinctrl-0 = <ð1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy1: ethernet-phy@7 {
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compatible = "ethernet-phy-id0022.1640",
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"ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupt-parent = <&irqc>;
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interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
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rxc-skew-psec = <2400>;
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txc-skew-psec = <2400>;
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rxdv-skew-psec = <0>;
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txen-skew-psec = <0>;
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rxd0-skew-psec = <0>;
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rxd1-skew-psec = <0>;
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rxd2-skew-psec = <0>;
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rxd3-skew-psec = <0>;
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txd0-skew-psec = <0>;
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txd1-skew-psec = <0>;
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txd2-skew-psec = <0>;
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txd3-skew-psec = <0>;
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};
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};
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&extal_clk {
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clock-frequency = <24000000>;
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};
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&ostm1 {
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status = "okay";
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};
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&ostm2 {
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status = "okay";
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};
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&pinctrl {
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adc_pins: adc {
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pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
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};
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eth0_pins: eth0 {
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pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
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<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
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<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
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<RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
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<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
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<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
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<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
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<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
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<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
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<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
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<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
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<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
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<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
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<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
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<RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
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<RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
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};
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eth1_pins: eth1 {
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pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
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<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
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<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
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<RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
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<RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
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<RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
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<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
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<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
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<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
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<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
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<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
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<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
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<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
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<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
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<RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
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<RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
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};
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sdhi0_emmc_pins: sd0emmc {
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sd0_emmc_data {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
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"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
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power-source = <1800>;
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};
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sd0_emmc_ctrl {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <1800>;
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};
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sd0_emmc_rst {
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pins = "SD0_RST#";
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power-source = <1800>;
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};
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};
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sdhi0_pins: sd0 {
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sd0_data {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
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power-source = <3300>;
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};
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sd0_ctrl {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <3300>;
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};
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sd0_mux {
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pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
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};
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};
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sdhi0_pins_uhs: sd0_uhs {
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sd0_data_uhs {
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pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
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power-source = <1800>;
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};
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sd0_ctrl_uhs {
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pins = "SD0_CLK", "SD0_CMD";
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power-source = <1800>;
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};
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sd0_mux_uhs {
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pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
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};
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};
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};
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#if (SW_SW0_DEV_SEL)
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&sdhi0 {
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pinctrl-0 = <&sdhi0_emmc_pins>;
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pinctrl-1 = <&sdhi0_emmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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#else
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <&vccq_sdhi0>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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#endif
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&wdt0 {
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status = "okay";
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timeout-sec = <60>;
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};
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