268 lines
7.2 KiB
C
268 lines
7.2 KiB
C
/* pci_fire.c: Sun4u platform PCI-E controller support.
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*
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* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include "pci_impl.h"
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#define fire_read(__reg) \
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({ u64 __ret; \
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__asm__ __volatile__("ldxa [%1] %2, %0" \
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: "=r" (__ret) \
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: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory"); \
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__ret; \
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})
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#define fire_write(__reg, __val) \
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__asm__ __volatile__("stxa %0, [%1] %2" \
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: /* no outputs */ \
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: "r" (__val), "r" (__reg), \
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"i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory")
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static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
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{
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pbm->pci_bus = pci_scan_one_pbm(pbm);
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/* XXX register error interrupt handlers XXX */
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}
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#define FIRE_IOMMU_CONTROL 0x40000UL
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#define FIRE_IOMMU_TSBBASE 0x40008UL
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#define FIRE_IOMMU_FLUSH 0x40100UL
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#define FIRE_IOMMU_FLUSHINV 0x40108UL
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static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
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{
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struct iommu *iommu = pbm->iommu;
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u32 vdma[2], dma_mask;
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u64 control;
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int tsbsize, err;
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/* No virtual-dma property on these guys, use largest size. */
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vdma[0] = 0xc0000000; /* base */
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vdma[1] = 0x40000000; /* size */
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dma_mask = 0xffffffff;
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tsbsize = 128;
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/* Register addresses. */
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iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
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iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
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iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
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iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
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/* We use the main control/status register of FIRE as the write
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* completion register.
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*/
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iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
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/*
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* Invalidate TLB Entries.
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*/
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fire_write(iommu->iommu_flushinv, ~(u64)0);
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err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
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if (err)
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return err;
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fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
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control = fire_read(iommu->iommu_control);
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control |= (0x00000400 /* TSB cache snoop enable */ |
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0x00000300 /* Cache mode */ |
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0x00000002 /* Bypass enable */ |
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0x00000001 /* Translation enable */);
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fire_write(iommu->iommu_control, control);
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return 0;
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}
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/* Based at pbm->controller_regs */
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#define FIRE_PARITY_CONTROL 0x470010UL
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#define FIRE_PARITY_ENAB 0x8000000000000000UL
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#define FIRE_FATAL_RESET_CTL 0x471028UL
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#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
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#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
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#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
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#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
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#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
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#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
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#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
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#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
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#define FIRE_CORE_INTR_ENABLE 0x471800UL
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/* Based at pbm->pbm_regs */
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#define FIRE_TLU_CTRL 0x80000UL
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#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
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#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
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#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
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#define FIRE_TLU_DEV_CTRL 0x90008UL
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#define FIRE_TLU_LINK_CTRL 0x90020UL
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#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
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#define FIRE_LPU_RESET 0xe2008UL
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#define FIRE_LPU_LLCFG 0xe2200UL
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#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
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#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
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#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
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#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
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#define FIRE_LPU_TXL_FIFOP 0xe2430UL
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#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
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#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
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#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
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#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
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#define FIRE_DMC_IENAB 0x31800UL
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#define FIRE_DMC_DBG_SEL_A 0x53000UL
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#define FIRE_DMC_DBG_SEL_B 0x53008UL
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#define FIRE_PEC_IENAB 0x51800UL
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static void pci_fire_hw_init(struct pci_pbm_info *pbm)
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{
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u64 val;
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fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
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FIRE_PARITY_ENAB);
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fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
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(FIRE_FATAL_RESET_SPARE |
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FIRE_FATAL_RESET_MB |
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FIRE_FATAL_RESET_CPE |
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FIRE_FATAL_RESET_APE |
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FIRE_FATAL_RESET_PIO |
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FIRE_FATAL_RESET_JW |
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FIRE_FATAL_RESET_JI |
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FIRE_FATAL_RESET_JR));
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fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
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val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
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val |= (FIRE_TLU_CTRL_TIM |
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FIRE_TLU_CTRL_QDET |
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FIRE_TLU_CTRL_CFG);
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fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
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fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
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fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
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FIRE_TLU_LINK_CTRL_CLK);
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fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
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fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
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FIRE_LPU_LLCFG_VC0);
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fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
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(FIRE_LPU_FCTRL_UCTRL_N |
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FIRE_LPU_FCTRL_UCTRL_P));
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fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
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((0xffff << 16) | (0x0000 << 0)));
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
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(2 << 16) | (140 << 8));
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fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
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fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
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fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
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fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
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fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
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}
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static int pci_fire_pbm_init(struct pci_controller_info *p,
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struct device_node *dp, u32 portid)
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{
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const struct linux_prom64_registers *regs;
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struct pci_pbm_info *pbm;
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if ((portid & 1) == 0)
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pbm = &p->pbm_A;
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else
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pbm = &p->pbm_B;
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pbm->next = pci_pbm_root;
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pci_pbm_root = pbm;
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pbm->scan_bus = pci_fire_scan_bus;
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pbm->pci_ops = &sun4u_pci_ops;
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pbm->config_space_reg_bits = 12;
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pbm->index = pci_num_pbms++;
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pbm->portid = portid;
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pbm->parent = p;
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pbm->prom_node = dp;
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pbm->name = dp->full_name;
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regs = of_get_property(dp, "reg", NULL);
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pbm->pbm_regs = regs[0].phys_addr;
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pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
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printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
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pci_determine_mem_io_space(pbm);
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pci_get_pbm_props(pbm);
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pci_fire_hw_init(pbm);
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return pci_fire_pbm_iommu_init(pbm);
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}
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static inline int portid_compare(u32 x, u32 y)
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{
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if (x == (y ^ 1))
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return 1;
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return 0;
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}
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void fire_pci_init(struct device_node *dp, const char *model_name)
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{
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struct pci_controller_info *p;
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u32 portid = of_getintprop_default(dp, "portid", 0xff);
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struct iommu *iommu;
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struct pci_pbm_info *pbm;
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for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
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if (portid_compare(pbm->portid, portid)) {
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if (pci_fire_pbm_init(pbm->parent, dp, portid))
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goto fatal_memory_error;
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return;
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}
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}
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p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
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if (!p)
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goto fatal_memory_error;
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iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
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if (!iommu)
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goto fatal_memory_error;
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p->pbm_A.iommu = iommu;
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iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
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if (!iommu)
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goto fatal_memory_error;
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p->pbm_B.iommu = iommu;
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/* XXX MSI support XXX */
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/* Like PSYCHO and SCHIZO we have a 2GB aligned area
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* for memory space.
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*/
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pci_memspace_mask = 0x7fffffffUL;
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if (pci_fire_pbm_init(p, dp, portid))
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goto fatal_memory_error;
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return;
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fatal_memory_error:
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prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
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prom_halt();
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}
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