fcc188e7fd
The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440 chips. To allow for this, this patch moves the definition of the ERPN used for mapping UART0 from being hard-coded in the head_44x.S assembly code to being defined in ibm44x.h. Signed-off-by: Roland Dreier <rolandd@cisco.com> Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> |
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| .. | ||
| Makefile | ||
| align.c | ||
| asm-offsets.c | ||
| cpu_setup_6xx.S | ||
| cpu_setup_power4.S | ||
| dma-mapping.c | ||
| entry.S | ||
| head.S | ||
| head_4xx.S | ||
| head_8xx.S | ||
| head_44x.S | ||
| head_booke.h | ||
| head_fsl_booke.S | ||
| idle.c | ||
| idle_6xx.S | ||
| idle_power4.S | ||
| irq.c | ||
| l2cr.S | ||
| machine_kexec.c | ||
| misc.S | ||
| module.c | ||
| pci.c | ||
| perfmon_fsl_booke.c | ||
| ppc-stub.c | ||
| ppc_htab.c | ||
| ppc_ksyms.c | ||
| process.c | ||
| relocate_kernel.S | ||
| semaphore.c | ||
| setup.c | ||
| smp-tbsync.c | ||
| smp.c | ||
| softemu8xx.c | ||
| swsusp.S | ||
| temp.c | ||
| time.c | ||
| traps.c | ||
| vmlinux.lds.S | ||