7aa1cc1091
If the Halo registers are kept in the register cache the HALO_CORE_RESET bit will be retained as 1 after reset is triggered in cs_dsp_halo_start_core. This will cause subsequent writes to reset the core which is not desired. Apart from this bit the rest of the register bits are cacheable, so for safety sake clear the bit to ensure the cache is consistent. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220105113026.18955-6-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org> |
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| cs_dsp.c | ||