original_kernel/drivers/clk/sunxi
Maxime Ripard 98b8525abb clk: sunxi: Add display and TCON0 clocks driver
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend), that have a lot in common with
the clock to drive the first TCON channel.

Add a driver to support both.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Silence variable sized array warning]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-12 14:47:52 -07:00
..
Makefile clk: sunxi: Add display and TCON0 clocks driver 2016-05-12 14:47:52 -07:00
clk-a10-codec.c
clk-a10-hosc.c clk: sunxi: Remove CLK_IS_ROOT 2016-04-15 16:50:05 -07:00
clk-a10-mod1.c clk: sunxi: mod1 clock should modify it's parent 2016-04-22 00:29:21 +02:00
clk-a10-pll2.c
clk-a10-ve.c clk: sunxi: Make reset_control_ops const 2016-03-29 16:30:07 -07:00
clk-a20-gmac.c
clk-factors.c
clk-factors.h
clk-mod0.c
clk-simple-gates.c
clk-sun4i-display.c clk: sunxi: Add display and TCON0 clocks driver 2016-05-12 14:47:52 -07:00
clk-sun4i-pll3.c clk: sunxi: Add PLL3 clock 2016-04-22 00:29:23 +02:00
clk-sun4i-tcon-ch1.c clk: sunxi: Add TCON channel1 clock 2016-04-22 00:29:24 +02:00
clk-sun6i-apb0-gates.c
clk-sun6i-apb0.c
clk-sun6i-ar100.c
clk-sun8i-apb0.c
clk-sun8i-bus-gates.c
clk-sun8i-mbus.c clk: sunxi: Remove use of variable length array 2016-03-15 15:15:27 -07:00
clk-sun9i-core.c
clk-sun9i-cpus.c
clk-sun9i-mmc.c Allwinner clocks additions for 4.7 2016-05-02 17:03:08 -07:00
clk-sunxi.c clk: sunxi: Let divs clocks read the base factor clock name from devicetree 2016-04-25 10:57:45 +02:00
clk-usb.c clk: sunxi: Make reset_control_ops const 2016-03-29 16:30:07 -07:00