131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Applied Micro X-Gene SoC MDIO Driver
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*
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* Copyright (c) 2016, Applied Micro Circuits Corporation
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* Author: Iyappan Subramanian <isubramanian@apm.com>
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*/
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#ifndef __MDIO_XGENE_H__
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#define __MDIO_XGENE_H__
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#define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
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#define BLOCK_DIAG_CSR_OFFSET 0xd000
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#define XGENET_CONFIG_REG_ADDR 0x20
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#define MAC_ADDR_REG_OFFSET 0x00
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#define MAC_COMMAND_REG_OFFSET 0x04
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#define MAC_WRITE_REG_OFFSET 0x08
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#define MAC_READ_REG_OFFSET 0x0c
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#define MAC_COMMAND_DONE_REG_OFFSET 0x10
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#define CLKEN_OFFSET 0x08
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#define SRST_OFFSET 0x00
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#define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
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#define MENET_BLOCK_MEM_RDY_ADDR 0x74
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#define MAC_CONFIG_1_ADDR 0x00
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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#define MII_MGMT_CONTROL_ADDR 0x2c
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#define MII_MGMT_STATUS_ADDR 0x30
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#define MII_MGMT_INDICATORS_ADDR 0x34
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#define SOFT_RESET BIT(31)
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#define MII_MGMT_CONFIG_ADDR 0x20
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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#define MII_MGMT_CONTROL_ADDR 0x2c
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#define MII_MGMT_STATUS_ADDR 0x30
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#define MII_MGMT_INDICATORS_ADDR 0x34
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#define MIIM_COMMAND_ADDR 0x20
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#define MIIM_FIELD_ADDR 0x24
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#define MIIM_CONFIGURATION_ADDR 0x28
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#define MIIM_LINKFAILVECTOR_ADDR 0x2c
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#define MIIM_INDICATOR_ADDR 0x30
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#define MIIMRD_FIELD_ADDR 0x34
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#define MDIO_CSR_OFFSET 0x5000
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#define REG_ADDR_POS 0
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#define REG_ADDR_LEN 5
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#define PHY_ADDR_POS 8
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#define PHY_ADDR_LEN 5
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#define HSTMIIMWRDAT_POS 0
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#define HSTMIIMWRDAT_LEN 16
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#define HSTPHYADX_POS 23
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#define HSTPHYADX_LEN 5
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#define HSTREGADX_POS 18
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#define HSTREGADX_LEN 5
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#define HSTLDCMD BIT(3)
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#define HSTMIIMCMD_POS 0
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#define HSTMIIMCMD_LEN 3
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#define BUSY_MASK BIT(0)
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#define READ_CYCLE_MASK BIT(0)
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enum xgene_enet_cmd {
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XGENE_ENET_WR_CMD = BIT(31),
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XGENE_ENET_RD_CMD = BIT(30)
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};
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enum {
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MIIM_CMD_IDLE,
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MIIM_CMD_LEGACY_WRITE,
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MIIM_CMD_LEGACY_READ,
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};
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enum xgene_mdio_id {
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XGENE_MDIO_RGMII = 1,
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XGENE_MDIO_XFI
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};
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struct xgene_mdio_pdata {
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struct clk *clk;
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struct device *dev;
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void __iomem *mac_csr_addr;
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void __iomem *diag_csr_addr;
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void __iomem *mdio_csr_addr;
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struct mii_bus *mdio_bus;
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int mdio_id;
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spinlock_t mac_lock; /* mac lock */
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};
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/* Set the specified value into a bit-field defined by its starting position
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* and length within a single u64.
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*/
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static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
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{
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return (val & ((1ULL << len) - 1)) << pos;
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}
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#define SET_VAL(field, val) \
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xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
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#define SET_BIT(field) \
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xgene_enet_set_field_value(field ## _POS, 1, 1)
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/* Get the value from a bit-field defined by its starting position
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* and length within the specified u64.
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*/
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static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
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{
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return (src >> pos) & ((1ULL << len) - 1);
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}
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#define GET_VAL(field, src) \
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xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
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#define GET_BIT(field, src) \
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xgene_enet_get_field_value(field ## _POS, 1, src)
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u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr);
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void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data);
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int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg);
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int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data);
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struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr);
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#endif /* __MDIO_XGENE_H__ */
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