492 lines
13 KiB
C
492 lines
13 KiB
C
/*
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* arch/ppc/platforms/cpci690.c
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*
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* Board setup routines for the Force CPCI690 board.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2003 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This programr
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/irq.h>
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#include <linux/fs.h>
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#include <linux/seq_file.h>
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#include <linux/console.h>
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#include <linux/initrd.h>
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#include <linux/root_dev.h>
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#include <linux/mv643xx.h>
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#include <asm/bootinfo.h>
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#include <asm/machdep.h>
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#include <asm/todc.h>
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#include <asm/time.h>
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#include <asm/mv64x60.h>
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#include <platforms/cpci690.h>
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#define BOARD_VENDOR "Force"
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#define BOARD_MACHINE "CPCI690"
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/* Set IDE controllers into Native mode? */
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#define SET_PCI_IDE_NATIVE
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static struct mv64x60_handle bh;
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static u32 cpci690_br_base;
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static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
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18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
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};
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TODC_ALLOC();
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static int __init
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cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
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if (hose->index == 0) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 90, 91, 88, 89}, /* IDSEL 30/20 - Sentinel */
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};
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const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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} else {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 93, 94, 95, 92}, /* IDSEL 28/18 - PMC slot 2 */
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{ 0, 0, 0, 0}, /* IDSEL 29/19 - Not used */
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{ 94, 95, 92, 93}, /* IDSEL 30/20 - PMC slot 1 */
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};
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const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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}
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static int
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cpci690_get_cpu_speed(void)
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{
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unsigned long hid1;
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hid1 = mfspr(SPRN_HID1) >> 28;
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return CPCI690_BUS_FREQ * cpu_7xx[hid1]/2;
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}
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#define KB (1024UL)
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#define MB (1024UL * KB)
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#define GB (1024UL * MB)
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unsigned long __init
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cpci690_find_end_of_memory(void)
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{
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u32 mem_ctlr_size;
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static u32 board_size;
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static u8 first_time = 1;
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if (first_time) {
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/* Using cpci690_set_bat() mapping ==> virt addr == phys addr */
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switch (in_8((u8 *) (cpci690_br_base +
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CPCI690_BR_MEM_CTLR)) & 0x07) {
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case 0x01:
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board_size = 256*MB;
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break;
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case 0x02:
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board_size = 512*MB;
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break;
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case 0x03:
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board_size = 768*MB;
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break;
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case 0x04:
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board_size = 1*GB;
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break;
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case 0x05:
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board_size = 1*GB + 512*MB;
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break;
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case 0x06:
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board_size = 2*GB;
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break;
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default:
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board_size = 0xffffffff; /* use mem ctlr size */
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} /* switch */
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mem_ctlr_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
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MV64x60_TYPE_GT64260A);
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/* Check that mem ctlr & board reg agree. If not, pick MIN. */
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if (board_size != mem_ctlr_size) {
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printk(KERN_WARNING "Board register & memory controller"
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"mem size disagree (board reg: 0x%lx, "
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"mem ctlr: 0x%lx)\n",
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(ulong)board_size, (ulong)mem_ctlr_size);
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board_size = min(board_size, mem_ctlr_size);
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}
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first_time = 0;
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} /* if */
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return board_size;
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}
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static void __init
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cpci690_setup_bridge(void)
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{
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struct mv64x60_setup_info si;
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int i;
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memset(&si, 0, sizeof(si));
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si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
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si.pci_0.enable_bus = 1;
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si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
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si.pci_0.pci_io.pci_base_hi = 0;
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si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
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si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
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si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
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si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
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si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
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si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
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si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
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si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
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si.pci_0.pci_cmd_bits = 0;
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si.pci_0.latency_timer = 0x80;
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si.pci_1.enable_bus = 1;
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si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
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si.pci_1.pci_io.pci_base_hi = 0;
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si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
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si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
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si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
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si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
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si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
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si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
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si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
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si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
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si.pci_1.pci_cmd_bits = 0;
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si.pci_1.latency_timer = 0x80;
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for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
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si.cpu_prot_options[i] = 0;
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si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
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si.pci_0.acc_cntl_options[i] =
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GT64260_PCI_ACC_CNTL_DREADEN |
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GT64260_PCI_ACC_CNTL_RDPREFETCH |
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GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
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GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
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GT64260_PCI_ACC_CNTL_SWAP_NONE |
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GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
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si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
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si.pci_1.acc_cntl_options[i] =
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GT64260_PCI_ACC_CNTL_DREADEN |
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GT64260_PCI_ACC_CNTL_RDPREFETCH |
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GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
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GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
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GT64260_PCI_ACC_CNTL_SWAP_NONE |
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GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
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si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
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}
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/* Lookup PCI host bridges */
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if (mv64x60_init(&bh, &si))
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printk(KERN_ERR "Bridge initialization failed.\n");
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pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = cpci690_map_irq;
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ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
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mv64x60_set_bus(&bh, 0, 0);
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bh.hose_a->first_busno = 0;
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bh.hose_a->last_busno = 0xff;
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bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
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bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
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mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
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bh.hose_b->last_busno = 0xff;
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bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
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bh.hose_b->first_busno);
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}
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static void __init
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cpci690_setup_peripherals(void)
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{
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/* Set up windows to CPLD, RTC/TODC, IPMI. */
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
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CPCI690_BR_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
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cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
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CPCI690_TODC_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
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TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
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ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);
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mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
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CPCI690_IPMI_SIZE, 0);
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bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
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mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
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mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
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mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
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/*
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* Turn off timer/counters. Not turning off watchdog timer because
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* can't read its reg on the 64260A so don't know if we'll be enabling
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* or disabling.
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*/
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mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
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((1<<0) | (1<<8) | (1<<16) | (1<<24)));
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mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
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((1<<0) | (1<<8) | (1<<16) | (1<<24)));
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/*
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* Set MPSC Multiplex RMII
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* NOTE: ethernet driver modifies bit 0 and 1
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*/
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mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
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#define GPP_EXTERNAL_INTERRUPTS \
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((1<<24) | (1<<25) | (1<<26) | (1<<27) | \
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(1<<28) | (1<<29) | (1<<30) | (1<<31))
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/* PCI interrupts are inputs */
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mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
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/* PCI interrupts are active low */
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mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
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/* Clear any pending interrupts for these inputs and enable them. */
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mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
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mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
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/* Route MPP interrupt inputs to GPP */
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mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
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mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
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}
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static void __init
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cpci690_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("cpci690_setup_arch: enter", 0);
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);
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/* Enable L2 and L3 caches (if 745x) */
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_set_L2CR(_get_L2CR() | L2CR_L2E);
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_set_L3CR(_get_L3CR() | L3CR_L3E);
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if (ppc_md.progress)
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ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);
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cpci690_setup_bridge(); /* set up PCI bridge(s) */
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cpci690_setup_peripherals(); /* set up chip selects/GPP/MPP etc */
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if (ppc_md.progress)
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ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);
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printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
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"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
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if (ppc_md.progress)
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ppc_md.progress("cpci690_setup_arch: exit", 0);
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}
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/* Platform device data fixup routines. */
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#if defined(CONFIG_SERIAL_MPSC)
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static void __init
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cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
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{
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struct mpsc_pdata *pdata;
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pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
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pdata->max_idle = 40;
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pdata->default_baud = CPCI690_MPSC_BAUD;
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pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
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pdata->brg_clk_freq = CPCI690_BUS_FREQ;
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}
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static int __init
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cpci690_platform_notify(struct device *dev)
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{
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static struct {
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char *bus_id;
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void ((*rtn)(struct platform_device *pdev));
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} dev_map[] = {
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{ MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
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{ MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
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};
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struct platform_device *pdev;
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int i;
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if (dev && dev->bus_id)
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for (i=0; i<ARRAY_SIZE(dev_map); i++)
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if (!strncmp(dev->bus_id, dev_map[i].bus_id,
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BUS_ID_SIZE)) {
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pdev = container_of(dev,
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struct platform_device, dev);
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dev_map[i].rtn(pdev);
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}
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return 0;
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}
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#endif
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static void
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cpci690_reset_board(void)
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{
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u32 i = 10000;
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local_irq_disable();
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out_8((u8 *)(cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
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while (i != 0) i++;
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panic("restart failed\n");
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}
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static void
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cpci690_restart(char *cmd)
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{
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cpci690_reset_board();
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}
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static void
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cpci690_halt(void)
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{
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while (1);
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/* NOTREACHED */
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}
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static void
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cpci690_power_off(void)
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{
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cpci690_halt();
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/* NOTREACHED */
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}
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static int
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cpci690_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
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seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
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seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000);
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seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000);
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return 0;
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}
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static void __init
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cpci690_calibrate_decr(void)
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{
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ulong freq;
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freq = CPCI690_BUS_FREQ / 4;
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printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
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freq/1000000, freq%1000000);
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tb_ticks_per_jiffy = freq / HZ;
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tb_to_us = mulhwu_scale_factor(freq, 1000000);
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}
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static __inline__ void
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cpci690_set_bat(u32 addr, u32 size)
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{
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addr &= 0xfffe0000;
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size &= 0x1ffe0000;
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size = ((size >> 17) - 1) << 2;
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mb();
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mtspr(SPRN_DBAT1U, addr | size | 0x2); /* Vs == 1; Vp == 0 */
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mtspr(SPRN_DBAT1L, addr | 0x2a); /* WIMG bits == 0101; PP == r/w access */
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mb();
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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static void __init
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cpci690_map_io(void)
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{
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io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
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128 * KB, _PAGE_IO);
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}
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#endif
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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#ifdef CONFIG_BLK_DEV_INITRD
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initrd_start=initrd_end=0;
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initrd_below_start_ok=0;
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#endif /* CONFIG_BLK_DEV_INITRD */
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parse_bootinfo(find_bootinfo());
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loops_per_jiffy = cpci690_get_cpu_speed() / HZ;
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isa_mem_base = 0;
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ppc_md.setup_arch = cpci690_setup_arch;
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ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
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ppc_md.init_IRQ = gt64260_init_irq;
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ppc_md.get_irq = gt64260_get_irq;
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ppc_md.restart = cpci690_restart;
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ppc_md.power_off = cpci690_power_off;
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ppc_md.halt = cpci690_halt;
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ppc_md.find_end_of_memory = cpci690_find_end_of_memory;
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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ppc_md.calibrate_decr = cpci690_calibrate_decr;
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/*
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* Need to map in board regs (used by cpci690_find_end_of_memory())
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* and the bridge's regs (used by progress);
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*/
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cpci690_set_bat(CPCI690_BR_BASE, 32 * MB);
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cpci690_br_base = CPCI690_BR_BASE;
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.setup_io_mappings = cpci690_map_io;
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ppc_md.progress = mv64x60_mpsc_progress;
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mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
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#endif /* CONFIG_SERIAL_TEXT_DEBUG */
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#ifdef CONFIG_KGDB
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ppc_md.setup_io_mappings = cpci690_map_io;
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ppc_md.early_serial_map = cpci690_early_serial_map;
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#endif /* CONFIG_KGDB */
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#if defined(CONFIG_SERIAL_MPSC)
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platform_notify = cpci690_platform_notify;
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#endif
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}
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