196 lines
6.6 KiB
C
196 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/mach-omap1/clock.h
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*
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* Copyright (C) 2004 - 2005, 2009 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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*/
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#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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struct module;
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struct omap1_clk;
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struct omap_clk {
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u16 cpu;
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struct clk_lookup lk;
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};
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#define CLK(dev, con, ck, cp) \
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{ \
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.cpu = cp, \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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.clk_hw = ck, \
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}, \
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}
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/* Platform flags for the clkdev-OMAP integration code */
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#define CK_310 (1 << 0)
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#define CK_7XX (1 << 1) /* 7xx, 850 */
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#define CK_1510 (1 << 2)
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#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
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#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
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/**
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* struct clkops - some clock function pointers
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* @enable: fn ptr that enables the current clock in hardware
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* @disable: fn ptr that enables the current clock in hardware
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* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
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*/
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struct clkops {
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int (*enable)(struct omap1_clk *clk);
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void (*disable)(struct omap1_clk *clk);
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};
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/*
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* struct clk.flags possibilities
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*
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* XXX document the rest of the clock flags here
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*/
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
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#define CLOCK_IDLE_CONTROL (1 << 1)
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#define CLOCK_NO_IDLE_PARENT (1 << 2)
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/**
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* struct omap1_clk - OMAP1 struct clk
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* @hw: struct clk_hw for common clock framework integration
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* @ops: struct clkops * for this clock
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* @rate: current clock rate
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* @enable_reg: register to write to enable the clock (see @enable_bit)
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* @recalc: fn ptr that returns the clock's current rate
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* @set_rate: fn ptr that can change the clock's current rate
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* @round_rate: fn ptr that can round the clock's current rate
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* @init: fn ptr to do clock-specific initialization
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
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* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
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* @flags: see "struct clk.flags possibilities" above
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* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
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*/
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struct omap1_clk {
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struct clk_hw hw;
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const struct clkops *ops;
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unsigned long rate;
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void __iomem *enable_reg;
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unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate);
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int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
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unsigned long p_rate);
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long (*round_rate)(struct omap1_clk *clk, unsigned long rate,
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unsigned long *p_rate);
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int (*init)(struct omap1_clk *clk);
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u8 enable_bit;
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u8 fixed_div;
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u8 flags;
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u8 rate_offset;
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};
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#define to_omap1_clk(_hw) container_of(_hw, struct omap1_clk, hw)
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void propagate_rate(struct omap1_clk *clk);
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unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate);
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unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate);
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extern struct omap1_clk dummy_ck;
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int omap1_clk_init(void);
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void omap1_clk_late_init(void);
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unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate);
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long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate);
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unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate);
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int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate,
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unsigned long p_rate);
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long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate);
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int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_init_ext_clk(struct omap1_clk *clk);
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int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
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int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
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long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate,
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unsigned long *p_rate);
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struct uart_clk {
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struct omap1_clk clk;
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unsigned long sysc_addr;
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};
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/* Provide a method for preventing idling some ARM IDLECT clocks */
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struct arm_idlect1_clk {
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struct omap1_clk clk;
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unsigned long no_idle_count;
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__u8 idlect_shift;
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};
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/* ARM_CKCTL bit shifts */
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#define CKCTL_PERDIV_OFFSET 0
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#define CKCTL_LCDDIV_OFFSET 2
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#define CKCTL_ARMDIV_OFFSET 4
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#define CKCTL_DSPDIV_OFFSET 6
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#define CKCTL_TCDIV_OFFSET 8
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#define CKCTL_DSPMMUDIV_OFFSET 10
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/*#define ARM_TIMXO 12*/
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#define EN_DSPCK 13
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/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
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/* DSP_CKCTL bit shifts */
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#define CKCTL_DSPPERDIV_OFFSET 0
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/* ARM_IDLECT2 bit shifts */
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#define EN_WDTCK 0
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#define EN_XORPCK 1
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#define EN_PERCK 2
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#define EN_LCDCK 3
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#define EN_LBCK 4 /* Not on 1610/1710 */
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/*#define EN_HSABCK 5*/
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#define EN_APICK 6
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#define EN_TIMCK 7
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#define DMACK_REQ 8
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#define EN_GPIOCK 9 /* Not on 1610/1710 */
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/*#define EN_LBFREECK 10*/
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#define EN_CKOUT_ARM 11
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/* ARM_IDLECT3 bit shifts */
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#define EN_OCPI_CK 0
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#define EN_TC1_CK 2
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#define EN_TC2_CK 4
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/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
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#define EN_DSPTIMCK 5
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/* Various register defines for clock controls scattered around OMAP chip */
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#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
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#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
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#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
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#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
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#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
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#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
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#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
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#define SOFT_REQ_REG 0xfffe0834
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#define SOFT_REQ_REG2 0xfffe0880
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extern __u32 arm_idlect1_mask;
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extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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extern const struct clkops clkops_dspck;
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extern const struct clkops clkops_uart_16xx;
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extern const struct clkops clkops_generic;
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/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
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extern u32 cpu_mask;
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extern const struct clk_ops omap1_clk_null_ops;
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extern const struct clk_ops omap1_clk_gate_ops;
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extern const struct clk_ops omap1_clk_rate_ops;
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extern const struct clk_ops omap1_clk_full_ops;
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#endif
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