181 lines
4.9 KiB
ArmAsm
181 lines
4.9 KiB
ArmAsm
/* linux/arch/arm/mach-s3c2410/sleep.S
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Power Manager (Suspend-To-RAM) support
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*
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* Based on PXA/SA1100 sleep code by:
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* Nicolas Pitre, (c) 2002 Monta Vista Software Inc
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* Cliff Brake, (c) 2001
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/hardware.h>
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#include <asm/arch/map.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-clock.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-serial.h>
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/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
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* reset the UART configuration, only enable if you really need this!
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*/
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//#define CONFIG_DEBUG_RESUME
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.text
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/* s3c2410_cpu_suspend
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*
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* put the cpu into sleep mode
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*
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* entry:
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* r0 = sleep save block
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*/
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ENTRY(s3c2410_cpu_suspend)
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stmfd sp!, { r4 - r12, lr }
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@@ store co-processor registers
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mrc p15, 0, r4, c15, c1, 0 @ CP access register
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mrc p15, 0, r5, c13, c0, 0 @ PID
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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mrc p15, 0, r7, c2, c0, 0 @ translation table base address
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mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register
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mrc p15, 0, r9, c1, c0, 0 @ control register
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stmia r0, { r4 - r13 }
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@@ flush the caches to ensure everything is back out to
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@@ SDRAM before the core powers down
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bl arm920_flush_kern_cache_all
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@@ prepare cpu to sleep
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ldr r4, =S3C2410_REFRESH
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ldr r5, =S3C2410_MISCCR
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ldr r6, =S3C2410_CLKCON
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ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
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ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
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ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
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orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
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orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
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orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
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teq pc, #0 @ first as a trial-run to load cache
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bl s3c2410_do_sleep
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teq r0, r0 @ now do it for real
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b s3c2410_do_sleep @
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@@ align next bit of code to cache line
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.align 8
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s3c2410_do_sleep:
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streq r7, [ r4 ] @ SDRAM sleep command
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streq r8, [ r5 ] @ SDRAM power-down config
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streq r9, [ r6 ] @ CPU sleep
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1: beq 1b
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mov pc, r14
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@@ return to the caller, after having the MMU
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@@ turned on, this restores the last bits from the
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@@ stack
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resume_with_mmu:
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ldmfd sp!, { r4 - r12, pc }
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.ltorg
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@@ the next bits sit in the .data segment, even though they
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@@ happen to be code... the s3c2410_sleep_save_phys needs to be
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@@ accessed by the resume code before it can restore the MMU.
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@@ This means that the variable has to be close enough for the
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@@ code to read it... since the .text segment needs to be RO,
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@@ the data segment can be the only place to put this code.
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.data
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.global s3c2410_sleep_save_phys
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s3c2410_sleep_save_phys:
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.word 0
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/* s3c2410_cpu_resume
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*
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* resume code entry for bootloader to call
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*
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* we must put this code here in the data segment as we have no
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* other way of restoring the stack pointer after sleep, and we
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* must not write to the code segment (code is read-only)
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*/
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ENTRY(s3c2410_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC
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msr cpsr_c, r0
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@@ load UART to allow us to print the two characters for
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@@ resume debug
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mov r2, #S3C2410_PA_UART & 0xff000000
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orr r2, r2, #S3C2410_PA_UART & 0xff000
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#if 0
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/* SMDK2440 LED set */
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mov r14, #S3C2410_PA_GPIO
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ldr r12, [ r14, #0x54 ]
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bic r12, r12, #3<<4
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orr r12, r12, #1<<7
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str r12, [ r14, #0x54 ]
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#endif
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#ifdef CONFIG_DEBUG_RESUME
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mov r3, #'L'
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strb r3, [ r2, #S3C2410_UTXH ]
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1001:
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ldrb r14, [ r3, #S3C2410_UTRSTAT ]
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tst r14, #S3C2410_UTRSTAT_TXE
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beq 1001b
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#endif /* CONFIG_DEBUG_RESUME */
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
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mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
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ldr r0, s3c2410_sleep_save_phys @ address of restore block
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ldmia r0, { r4 - r13 }
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mcr p15, 0, r4, c15, c1, 0 @ CP access register
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mcr p15, 0, r5, c13, c0, 0 @ PID
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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mcr p15, 0, r7, c2, c0, 0 @ translation table base
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mcr p15, 0, r8, c1, c1, 0 @ auxilliary control
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#ifdef CONFIG_DEBUG_RESUME
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mov r3, #'R'
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strb r3, [ r2, #S3C2410_UTXH ]
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#endif
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ldr r2, =resume_with_mmu
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mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
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nop @ second-to-last before mmu
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mov pc, r2 @ go back to virtual address
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.ltorg
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