82622284dd
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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.. | ||
alchemy | ||
ar7 | ||
basler/excite | ||
bcm47xx | ||
bcm63xx | ||
boot | ||
cavium-octeon | ||
cobalt | ||
configs | ||
dec | ||
emma | ||
fw | ||
gt64120/wrppmc | ||
include/asm | ||
jazz | ||
kernel | ||
lasat | ||
lib | ||
loongson | ||
math-emu | ||
mipssim | ||
mm | ||
mti-malta | ||
nxp | ||
oprofile | ||
pci | ||
pmc-sierra | ||
power | ||
rb532 | ||
sgi-ip22 | ||
sgi-ip27 | ||
sgi-ip32 | ||
sibyte | ||
sni | ||
txx9 | ||
vr41xx | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |