205 lines
6.9 KiB
C
205 lines
6.9 KiB
C
/*
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* ibm_ocp.h
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*
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* (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
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* Mipsys - France
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*
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* Derived from work (c) Armin Kuster akuster@pacbell.net
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*
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* Additional support and port to 2.6 LDM/sysfs by
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2003-2004 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __IBM_OCP_H__
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#define __IBM_OCP_H__
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#include <asm/types.h>
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/*
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* IBM 4xx OCP system information
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*/
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struct ocp_sys_info_data {
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int opb_bus_freq; /* OPB Bus Frequency (Hz) */
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int ebc_bus_freq; /* EBC Bus Frequency (Hz) */
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};
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extern struct ocp_sys_info_data ocp_sys_info;
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/*
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* EMAC additional data and sysfs support
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*
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* Note about mdio_idx: When you have a zmii, it's usually
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* not necessary, it covers the case of the 405EP which has
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* the MDIO lines on EMAC0 only
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*
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* Note about phy_map: Per EMAC map of PHY ids which should
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* be probed by emac_probe. Different EMACs can have
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* overlapping maps.
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*
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* Note, this map uses inverse logic for bits:
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* 0 - id should be probed
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* 1 - id should be ignored
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*
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* Default value of 0x00000000 - will result in usual
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* auto-detection logic.
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*
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*/
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struct ocp_func_emac_data {
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int rgmii_idx; /* RGMII device index or -1 */
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int rgmii_mux; /* RGMII input of this EMAC */
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int zmii_idx; /* ZMII device index or -1 */
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int zmii_mux; /* ZMII input of this EMAC */
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int mal_idx; /* MAL device index */
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int mal_rx_chan; /* MAL rx channel number */
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int mal_tx_chan; /* MAL tx channel number */
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int wol_irq; /* WOL interrupt */
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int mdio_idx; /* EMAC idx of MDIO master or -1 */
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int tah_idx; /* TAH device index or -1 */
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int phy_mode; /* PHY type or configurable mode */
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u8 mac_addr[6]; /* EMAC mac address */
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u32 phy_map; /* EMAC phy map */
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u32 phy_feat_exc; /* Excluded PHY features */
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};
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/* Sysfs support */
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#define OCP_SYSFS_EMAC_DATA() \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \
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OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\
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\
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void ocp_show_emac_data(struct device *dev) \
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{ \
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device_create_file(dev, &dev_attr_emac_rgmii_idx); \
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device_create_file(dev, &dev_attr_emac_rgmii_mux); \
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device_create_file(dev, &dev_attr_emac_zmii_idx); \
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device_create_file(dev, &dev_attr_emac_zmii_mux); \
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device_create_file(dev, &dev_attr_emac_mal_idx); \
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device_create_file(dev, &dev_attr_emac_mal_rx_chan); \
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device_create_file(dev, &dev_attr_emac_mal_tx_chan); \
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device_create_file(dev, &dev_attr_emac_wol_irq); \
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device_create_file(dev, &dev_attr_emac_mdio_idx); \
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device_create_file(dev, &dev_attr_emac_tah_idx); \
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device_create_file(dev, &dev_attr_emac_phy_mode); \
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device_create_file(dev, &dev_attr_emac_phy_map); \
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device_create_file(dev, &dev_attr_emac_phy_feat_exc); \
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}
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/*
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* PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
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*/
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#define PHY_MODE_NA 0
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#define PHY_MODE_MII 1
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#define PHY_MODE_RMII 2
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#define PHY_MODE_SMII 3
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#define PHY_MODE_RGMII 4
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#define PHY_MODE_TBI 5
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#define PHY_MODE_GMII 6
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#define PHY_MODE_RTBI 7
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#define PHY_MODE_SGMII 8
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#ifdef CONFIG_40x
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/*
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* Helper function to copy MAC addresses from the bd_t to OCP EMAC
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* additions.
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*
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* The range of EMAC indices (inclusive) to be copied are the arguments.
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*/
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static inline void ibm_ocp_set_emac(int start, int end)
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{
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int i;
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struct ocp_def *def;
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/* Copy MAC addresses to EMAC additions */
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for (i=start; i<=end; i++) {
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
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if (i == 0)
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memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
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__res.bi_enetaddr, 6);
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#if defined(CONFIG_405EP) || defined(CONFIG_44x)
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else if (i == 1)
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memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
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__res.bi_enet1addr, 6);
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#endif
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#if defined(CONFIG_440GX)
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else if (i == 2)
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memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
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__res.bi_enet2addr, 6);
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else if (i == 3)
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memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
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__res.bi_enet3addr, 6);
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#endif
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}
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}
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#endif
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/*
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* MAL additional data and sysfs support
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*/
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struct ocp_func_mal_data {
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int num_tx_chans; /* Number of TX channels */
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int num_rx_chans; /* Number of RX channels */
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int txeob_irq; /* TX End Of Buffer IRQ */
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int rxeob_irq; /* RX End Of Buffer IRQ */
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int txde_irq; /* TX Descriptor Error IRQ */
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int rxde_irq; /* RX Descriptor Error IRQ */
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int serr_irq; /* MAL System Error IRQ */
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int dcr_base; /* MALx_CFG DCR number */
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};
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#define OCP_SYSFS_MAL_DATA() \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \
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OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \
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\
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void ocp_show_mal_data(struct device *dev) \
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{ \
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device_create_file(dev, &dev_attr_mal_num_tx_chans); \
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device_create_file(dev, &dev_attr_mal_num_rx_chans); \
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device_create_file(dev, &dev_attr_mal_txeob_irq); \
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device_create_file(dev, &dev_attr_mal_rxeob_irq); \
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device_create_file(dev, &dev_attr_mal_txde_irq); \
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device_create_file(dev, &dev_attr_mal_rxde_irq); \
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device_create_file(dev, &dev_attr_mal_serr_irq); \
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device_create_file(dev, &dev_attr_mal_dcr_base); \
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}
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/*
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* IIC additional data and sysfs support
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*/
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struct ocp_func_iic_data {
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int fast_mode; /* IIC fast mode enabled */
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};
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#define OCP_SYSFS_IIC_DATA() \
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OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \
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\
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void ocp_show_iic_data(struct device *dev) \
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{ \
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device_create_file(dev, &dev_attr_iic_fast_mode); \
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}
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#endif /* __IBM_OCP_H__ */
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#endif /* __KERNEL__ */
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