164 lines
4.1 KiB
ArmAsm
164 lines
4.1 KiB
ArmAsm
/*
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*
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* Trampoline.S Derived from Setup.S by Linus Torvalds
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*
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* 4 Jan 1997 Michael Chastain: changed to gnu as.
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* 15 Sept 2005 Eric Biederman: 64bit PIC support
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*
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* Entry: CS:IP point to the start of our code, we are
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* in real mode with no stack, but the rest of the
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* trampoline page to make our stack and everything else
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* is a mystery.
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*
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* On entry to trampoline_data, the processor is in real mode
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* with 16-bit addressing and 16-bit data. CS has some value
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* and IP is zero. Thus, data addresses need to be absolute
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* (no relocation) and are taken with regard to r_base.
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*
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* With the addition of trampoline_level4_pgt this code can
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* now enter a 64bit kernel that lives at arbitrary 64bit
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* physical addresses.
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*
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* If you work on this file, check the object module with objdump
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* --full-contents --reloc to make sure there are no relocation
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* entries.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/pgtable_types.h>
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#include <asm/page_types.h>
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#include <asm/msr.h>
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#include <asm/segment.h>
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#include <asm/processor-flags.h>
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/* We can free up the trampoline after bootup if cpu hotplug is not supported. */
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__CPUINITRODATA
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.code16
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ENTRY(trampoline_data)
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r_base = .
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cli # We should be safe anyway
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wbinvd
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mov %cs, %ax # Code and data in the same place
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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movl $0xA5A5A5A5, trampoline_data - r_base
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# write marker for master knows we're running
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# Setup stack
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movw $(trampoline_stack_end - r_base), %sp
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call verify_cpu # Verify the cpu supports long mode
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testl %eax, %eax # Check for return code
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jnz no_longmode
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mov %cs, %ax
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movzx %ax, %esi # Find the 32bit trampoline location
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shll $4, %esi
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# Fixup the vectors
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addl %esi, startup_32_vector - r_base
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addl %esi, startup_64_vector - r_base
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addl %esi, tgdt + 2 - r_base # Fixup the gdt pointer
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/*
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* GDT tables in non default location kernel can be beyond 16MB and
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* lgdt will not be able to load the address as in real mode default
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* operand size is 16bit. Use lgdtl instead to force operand size
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* to 32 bit.
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*/
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lidtl tidt - r_base # load idt with 0, 0
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lgdtl tgdt - r_base # load gdt with whatever is appropriate
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mov $X86_CR0_PE, %ax # protected mode (PE) bit
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lmsw %ax # into protected mode
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# flush prefetch and jump to startup_32
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ljmpl *(startup_32_vector - r_base)
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.code32
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.balign 4
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startup_32:
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movl $__KERNEL_DS, %eax # Initialize the %ds segment register
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movl %eax, %ds
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movl $X86_CR4_PAE, %eax
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movl %eax, %cr4 # Enable PAE mode
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# Setup trampoline 4 level pagetables
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leal (trampoline_level4_pgt - r_base)(%esi), %eax
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movl %eax, %cr3
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movl $MSR_EFER, %ecx
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movl $(1 << _EFER_LME), %eax # Enable Long Mode
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xorl %edx, %edx
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wrmsr
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# Enable paging and in turn activate Long Mode
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# Enable protected mode
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movl $(X86_CR0_PG | X86_CR0_PE), %eax
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movl %eax, %cr0
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/*
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* At this point we're in long mode but in 32bit compatibility mode
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* with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
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* EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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*/
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ljmp *(startup_64_vector - r_base)(%esi)
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.code64
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.balign 4
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startup_64:
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# Now jump into the kernel using virtual addresses
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movq $secondary_startup_64, %rax
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jmp *%rax
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.code16
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no_longmode:
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hlt
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jmp no_longmode
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#include "verify_cpu_64.S"
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# Careful these need to be in the same 64K segment as the above;
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tidt:
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.word 0 # idt limit = 0
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.word 0, 0 # idt base = 0L
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# Duplicate the global descriptor table
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# so the kernel can live anywhere
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.balign 4
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tgdt:
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.short tgdt_end - tgdt # gdt limit
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.long tgdt - r_base
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.short 0
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.quad 0x00cf9b000000ffff # __KERNEL32_CS
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.quad 0x00af9b000000ffff # __KERNEL_CS
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.quad 0x00cf93000000ffff # __KERNEL_DS
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tgdt_end:
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.balign 4
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startup_32_vector:
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.long startup_32 - r_base
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.word __KERNEL32_CS, 0
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.balign 4
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startup_64_vector:
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.long startup_64 - r_base
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.word __KERNEL_CS, 0
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trampoline_stack:
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.org 0x1000
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trampoline_stack_end:
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ENTRY(trampoline_level4_pgt)
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.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
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.fill 510,8,0
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.quad level3_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
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ENTRY(trampoline_end)
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