336 lines
7.2 KiB
C
336 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SMP Support
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*
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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* Copyright (C) 1999, 2001, 2003 David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* Lots of stuff stolen from arch/alpha/kernel/smp.c
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*
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* 01/05/16 Rohit Seth <rohit.seth@intel.com> IA64-SMP functions. Reorganized
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* the existing code (on the lines of x86 port).
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* 00/09/11 David Mosberger <davidm@hpl.hp.com> Do loops_per_jiffy
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* calibration on each CPU.
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* 00/08/23 Asit Mallick <asit.k.mallick@intel.com> fixed logical processor id
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* 00/03/31 Rohit Seth <rohit.seth@intel.com> Fixes for Bootstrap Processor
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* & cpu_online_map now gets done here (instead of setup.c)
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* 99/10/05 davidm Update to bring it in sync with new command-line processing
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* scheme.
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* 10/13/00 Goutham Rao <goutham.rao@intel.com> Updated smp_call_function and
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* smp_call_function_single to resend IPI on timeouts
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <linux/mm.h>
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/efi.h>
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#include <linux/bitops.h>
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#include <linux/kexec.h>
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#include <linux/atomic.h>
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#include <asm/current.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/sal.h>
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#include <asm/tlbflush.h>
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#include <asm/unistd.h>
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#include <asm/mca.h>
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#include <asm/xtp.h>
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/*
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* Note: alignment of 4 entries/cacheline was empirically determined
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* to be a good tradeoff between hot cachelines & spreading the array
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* across too many cacheline.
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*/
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static struct local_tlb_flush_counts {
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unsigned int count;
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} __attribute__((__aligned__(32))) local_tlb_flush_counts[NR_CPUS];
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static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned short [NR_CPUS],
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shadow_flush_counts);
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#define IPI_CALL_FUNC 0
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#define IPI_CPU_STOP 1
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#define IPI_CALL_FUNC_SINGLE 2
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#define IPI_KDUMP_CPU_STOP 3
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/* This needs to be cacheline aligned because it is written to by *other* CPUs. */
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static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, ipi_operation);
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extern void cpu_halt (void);
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static void
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stop_this_cpu(void)
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{
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/*
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* Remove this CPU:
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*/
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set_cpu_online(smp_processor_id(), false);
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max_xtp();
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local_irq_disable();
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cpu_halt();
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}
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void
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cpu_die(void)
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{
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max_xtp();
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local_irq_disable();
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cpu_halt();
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/* Should never be here */
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BUG();
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for (;;);
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}
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irqreturn_t
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handle_IPI (int irq, void *dev_id)
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{
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int this_cpu = get_cpu();
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unsigned long *pending_ipis = &__ia64_per_cpu_var(ipi_operation);
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unsigned long ops;
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mb(); /* Order interrupt and bit testing. */
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while ((ops = xchg(pending_ipis, 0)) != 0) {
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mb(); /* Order bit clearing and data access. */
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do {
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unsigned long which;
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which = ffz(~ops);
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ops &= ~(1 << which);
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switch (which) {
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case IPI_CPU_STOP:
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stop_this_cpu();
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break;
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case IPI_CALL_FUNC:
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generic_smp_call_function_interrupt();
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break;
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case IPI_CALL_FUNC_SINGLE:
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generic_smp_call_function_single_interrupt();
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break;
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#ifdef CONFIG_KEXEC
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case IPI_KDUMP_CPU_STOP:
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unw_init_running(kdump_cpu_freeze, NULL);
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break;
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#endif
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default:
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printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n",
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this_cpu, which);
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break;
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}
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} while (ops);
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mb(); /* Order data access and bit testing. */
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}
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put_cpu();
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return IRQ_HANDLED;
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}
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/*
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* Called with preemption disabled.
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*/
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static inline void
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send_IPI_single (int dest_cpu, int op)
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{
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set_bit(op, &per_cpu(ipi_operation, dest_cpu));
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ia64_send_ipi(dest_cpu, IA64_IPI_VECTOR, IA64_IPI_DM_INT, 0);
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}
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/*
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* Called with preemption disabled.
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*/
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static inline void
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send_IPI_allbutself (int op)
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{
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unsigned int i;
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for_each_online_cpu(i) {
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if (i != smp_processor_id())
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send_IPI_single(i, op);
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}
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}
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/*
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* Called with preemption disabled.
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*/
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static inline void
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send_IPI_mask(const struct cpumask *mask, int op)
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{
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unsigned int cpu;
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for_each_cpu(cpu, mask) {
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send_IPI_single(cpu, op);
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}
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}
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/*
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* Called with preemption disabled.
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*/
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static inline void
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send_IPI_all (int op)
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{
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int i;
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for_each_online_cpu(i) {
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send_IPI_single(i, op);
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}
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}
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/*
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* Called with preemption disabled.
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*/
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static inline void
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send_IPI_self (int op)
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{
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send_IPI_single(smp_processor_id(), op);
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}
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#ifdef CONFIG_KEXEC
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void
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kdump_smp_send_stop(void)
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{
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send_IPI_allbutself(IPI_KDUMP_CPU_STOP);
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}
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void
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kdump_smp_send_init(void)
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{
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unsigned int cpu, self_cpu;
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self_cpu = smp_processor_id();
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for_each_online_cpu(cpu) {
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if (cpu != self_cpu) {
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if(kdump_status[cpu] == 0)
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ia64_send_ipi(cpu, 0, IA64_IPI_DM_INIT, 0);
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}
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}
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}
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#endif
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/*
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* Called with preemption disabled.
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*/
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void
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smp_send_reschedule (int cpu)
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{
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ia64_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0);
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}
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EXPORT_SYMBOL_GPL(smp_send_reschedule);
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/*
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* Called with preemption disabled.
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*/
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static void
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smp_send_local_flush_tlb (int cpu)
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{
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ia64_send_ipi(cpu, IA64_IPI_LOCAL_TLB_FLUSH, IA64_IPI_DM_INT, 0);
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}
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void
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smp_local_flush_tlb(void)
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{
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/*
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* Use atomic ops. Otherwise, the load/increment/store sequence from
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* a "++" operation can have the line stolen between the load & store.
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* The overhead of the atomic op in negligible in this case & offers
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* significant benefit for the brief periods where lots of cpus
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* are simultaneously flushing TLBs.
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*/
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ia64_fetchadd(1, &local_tlb_flush_counts[smp_processor_id()].count, acq);
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local_flush_tlb_all();
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}
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#define FLUSH_DELAY 5 /* Usec backoff to eliminate excessive cacheline bouncing */
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void
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smp_flush_tlb_cpumask(cpumask_t xcpumask)
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{
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unsigned short *counts = __ia64_per_cpu_var(shadow_flush_counts);
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cpumask_t cpumask = xcpumask;
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int mycpu, cpu, flush_mycpu = 0;
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preempt_disable();
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mycpu = smp_processor_id();
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for_each_cpu(cpu, &cpumask)
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counts[cpu] = local_tlb_flush_counts[cpu].count & 0xffff;
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mb();
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for_each_cpu(cpu, &cpumask) {
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if (cpu == mycpu)
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flush_mycpu = 1;
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else
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smp_send_local_flush_tlb(cpu);
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}
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if (flush_mycpu)
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smp_local_flush_tlb();
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for_each_cpu(cpu, &cpumask)
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while(counts[cpu] == (local_tlb_flush_counts[cpu].count & 0xffff))
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udelay(FLUSH_DELAY);
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preempt_enable();
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}
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void
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smp_flush_tlb_all (void)
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{
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on_each_cpu((void (*)(void *))local_flush_tlb_all, NULL, 1);
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}
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void
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smp_flush_tlb_mm (struct mm_struct *mm)
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{
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cpumask_var_t cpus;
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preempt_disable();
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/* this happens for the common case of a single-threaded fork(): */
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if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1))
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{
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local_finish_flush_tlb_mm(mm);
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preempt_enable();
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return;
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}
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if (!alloc_cpumask_var(&cpus, GFP_ATOMIC)) {
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smp_call_function((void (*)(void *))local_finish_flush_tlb_mm,
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mm, 1);
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} else {
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cpumask_copy(cpus, mm_cpumask(mm));
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smp_call_function_many(cpus,
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(void (*)(void *))local_finish_flush_tlb_mm, mm, 1);
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free_cpumask_var(cpus);
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}
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local_irq_disable();
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local_finish_flush_tlb_mm(mm);
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local_irq_enable();
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preempt_enable();
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}
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void arch_send_call_function_single_ipi(int cpu)
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{
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send_IPI_single(cpu, IPI_CALL_FUNC_SINGLE);
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}
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void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
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send_IPI_mask(mask, IPI_CALL_FUNC);
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}
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/*
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* this function calls the 'stop' function on all other CPUs in the system.
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*/
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void
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smp_send_stop (void)
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{
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send_IPI_allbutself(IPI_CPU_STOP);
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}
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