274 lines
6.1 KiB
C
274 lines
6.1 KiB
C
/*arch/ppc/platforms/mpc885ads-setup.c
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*
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* Platform setup for the Freescale mpc885ads board
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*
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/mii.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/ppcboot.h>
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#include <asm/8xx_immap.h>
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#include <asm/commproc.h>
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#include <asm/ppc_sys.h>
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#include <asm/mpc8xx.h>
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extern unsigned char __res[];
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static struct fs_mii_bus_info fec_mii_bus_info = {
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.method = fsmii_fec,
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.id = 0,
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};
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static struct fs_mii_bus_info scc_mii_bus_info = {
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.method = fsmii_fixed,
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.id = 0,
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.i.fixed.speed = 10,
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.i.fixed.duplex = 0,
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};
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static struct fs_platform_info mpc8xx_fec_pdata[] = {
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{
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.phy_addr = 15,
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.phy_irq = -1,
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.use_rmii = 0,
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.bus_info = &fec_mii_bus_info,
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}
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};
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static struct fs_platform_info mpc8xx_scc_pdata = {
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.rx_ring = 64,
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.tx_ring = 8,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.phy_addr = -1,
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.phy_irq = -1,
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.bus_info = &scc_mii_bus_info,
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};
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void __init board_init(void)
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{
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volatile cpm8xx_t *cp = cpmp;
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unsigned *bcsr_io;
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR1\n");
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return;
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}
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#ifdef CONFIG_SERIAL_CPM_SMC1
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cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
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clrbits32(bcsr_io,(0x80000000 >> 7));
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#else
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setbits32(bcsr_io,(0x80000000 >> 7));
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cp->cp_pbpar &= ~(0x000000c0);
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cp->cp_pbdir |= 0x000000c0;
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cp->cp_smc[0].smc_smcmr = 0;
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cp->cp_smc[0].smc_smce = 0;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC2
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cp->cp_simode &= ~(0xe0000000 >> 1);
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cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
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clrbits32(bcsr_io,(0x80000000 >> 13));
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#else
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clrbits32(bcsr_io,(0x80000000 >> 13));
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cp->cp_pbpar &= ~(0x00000c00);
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cp->cp_pbdir |= 0x00000c00;
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cp->cp_smc[1].smc_smcmr = 0;
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cp->cp_smc[1].smc_smce = 0;
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#endif
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iounmap(bcsr_io);
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}
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static void setup_fec1_ioports(void)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
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setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
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}
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static void setup_scc1_ioports(void)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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unsigned *bcsr_io;
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR1\n");
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return;
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}
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/* Enable the PHY.
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*/
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clrbits32(bcsr_io,BCSR1_ETHEN);
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/* Configure port A pins for Txd and Rxd.
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*/
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/* Disable receive and transmit in case EPPC-Bug started it.
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*/
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setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
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clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
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clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
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/* Configure port C pins to enable CLSN and RENA.
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*/
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clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
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clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
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setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
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/* Configure port A for TCLK and RCLK.
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*/
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setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
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clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
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clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
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clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
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/* Configure Serial Interface clock routing.
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* First, clear all SCC bits to zero, then set the ones we want.
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*/
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clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
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setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
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/* In the original SCC enet driver the following code is placed at
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the end of the initialization */
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setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
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setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
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}
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static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
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{
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struct fs_platform_info *fpi = pdev->dev.platform_data;
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volatile cpm8xx_t *cp;
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bd_t *bd = (bd_t *) __res;
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char *e;
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int i;
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/* Get pointer to Communication Processor */
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cp = cpmp;
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switch (fs_no) {
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case fsid_fec1:
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fpi = &mpc8xx_fec_pdata[0];
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fpi->init_ioports = &setup_fec1_ioports;
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break;
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case fsid_scc1:
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fpi = &mpc8xx_scc_pdata;
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fpi->init_ioports = &setup_scc1_ioports;
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break;
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default:
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printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
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return;
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}
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pdev->dev.platform_data = fpi;
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fpi->fs_no = fs_no;
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e = (unsigned char *)&bd->bi_enetaddr;
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for (i = 0; i < 6; i++)
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fpi->macaddr[i] = *e++;
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fpi->macaddr[5 - pdev->id]++;
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}
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static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
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int idx)
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{
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/* This is for FEC devices only */
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if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
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return;
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mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
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}
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static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
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int idx)
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{
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/* This is for SCC devices only */
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if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
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return;
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mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
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}
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static int mpc866ads_platform_notify(struct device *dev)
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{
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static const struct platform_notify_dev_map dev_map[] = {
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{
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.bus_id = "fsl-cpm-fec",
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.rtn = mpc866ads_fixup_fec_enet_pdata,
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},
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{
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.bus_id = "fsl-cpm-scc",
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.rtn = mpc866ads_fixup_scc_enet_pdata,
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},
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{
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.bus_id = NULL
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}
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};
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platform_notify_map(dev_map,dev);
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return 0;
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}
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int __init mpc866ads_init(void)
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{
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printk(KERN_NOTICE "mpc866ads: Init\n");
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platform_notify = mpc866ads_platform_notify;
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ppc_sys_device_initfunc();
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ppc_sys_device_disable_all();
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#ifdef MPC8xx_SECOND_ETH_SCC1
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ppc_sys_device_enable(MPC8xx_CPM_SCC1);
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#endif
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ppc_sys_device_enable(MPC8xx_CPM_FEC1);
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return 0;
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}
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arch_initcall(mpc866ads_init);
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