851 lines
21 KiB
C
851 lines
21 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org)
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* Copyright (c) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_BITOPS_H
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#define _ASM_BITOPS_H
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/byteorder.h> /* sigh ... */
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#include <asm/cpu-features.h>
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#if (_MIPS_SZLONG == 32)
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#define SZLONG_LOG 5
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#define SZLONG_MASK 31UL
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#define __LL "ll "
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#define __SC "sc "
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#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
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#elif (_MIPS_SZLONG == 64)
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#define SZLONG_LOG 6
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#define SZLONG_MASK 63UL
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#define __LL "lld "
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#define __SC "scd "
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#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
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#endif
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#ifdef __KERNEL__
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#include <asm/interrupt.h>
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#include <asm/sgidefs.h>
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#include <asm/war.h>
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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/*
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* Only disable interrupt for kernel mode stuff to keep usermode stuff
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* that dares to use kernel include files alive.
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*/
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#define __bi_flags unsigned long flags
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#define __bi_local_irq_save(x) local_irq_save(x)
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#define __bi_local_irq_restore(x) local_irq_restore(x)
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#else
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#define __bi_flags
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#define __bi_local_irq_save(x)
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#define __bi_local_irq_restore(x)
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#endif /* __KERNEL__ */
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/*
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # set_bit \n"
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" or %0, %2 \n"
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" "__SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # set_bit \n"
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" or %0, %2 \n"
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" "__SC "%0, %1 \n"
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" beqz %0, 1b \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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*a |= mask;
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__bi_local_irq_restore(flags);
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}
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}
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/*
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __set_bit(unsigned long nr, volatile unsigned long * addr)
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{
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unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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*m |= 1UL << (nr & SZLONG_MASK);
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}
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/*
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # clear_bit \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # clear_bit \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 1b \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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*a &= ~mask;
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__bi_local_irq_restore(flags);
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}
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}
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/*
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* __clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* Unlike clear_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr)
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{
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unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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*m &= ~(1UL << (nr & SZLONG_MASK));
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}
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/*
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # change_bit \n"
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" xor %0, %2 \n"
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" "__SC "%0, %1 \n"
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" beqzl %0, 1b \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # change_bit \n"
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" xor %0, %2 \n"
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" "__SC "%0, %1 \n"
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" beqz %0, 1b \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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*a ^= mask;
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__bi_local_irq_restore(flags);
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}
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}
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/*
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __change_bit(unsigned long nr, volatile unsigned long * addr)
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{
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unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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*m ^= 1UL << (nr & SZLONG_MASK);
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}
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/*
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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"sync \n"
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#endif
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set noreorder # test_and_set_bit \n"
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"1: " __LL "%0, %1 \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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"sync \n"
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#endif
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".set\treorder"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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int retval;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a |= mask;
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__bi_local_irq_restore(flags);
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return retval;
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}
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}
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/*
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr;
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unsigned long mask;
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int retval;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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retval = (mask & *a) != 0;
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*a |= mask;
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return retval;
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}
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/*
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # test_and_clear_bit \n"
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" or %2, %0, %3 \n"
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" xor %2, %3 \n"
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__SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set noreorder # test_and_clear_bit \n"
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"1: " __LL "%0, %1 \n"
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" or %2, %0, %3 \n"
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" xor %2, %3 \n"
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__SC "%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set reorder \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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int retval;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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__bi_local_irq_restore(flags);
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return retval;
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}
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}
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/*
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_clear_bit(unsigned long nr,
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volatile unsigned long * addr)
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{
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volatile unsigned long *a = addr;
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unsigned long mask;
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int retval;
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a += (nr >> SZLONG_LOG);
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mask = 1UL << (nr & SZLONG_MASK);
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retval = ((mask & *a) != 0);
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*a &= ~mask;
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return retval;
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}
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/*
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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"1: " __LL " %0, %1 # test_and_change_bit \n"
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" xor %2, %0, %3 \n"
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" "__SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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" .set noreorder # test_and_change_bit \n"
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"1: " __LL " %0, %1 \n"
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" xor %2, %0, %3 \n"
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" "__SC "\t%2, %1 \n"
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" beqz %2, 1b \n"
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" and %2, %0, %3 \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" .set reorder \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "memory");
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return res != 0;
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask, retval;
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__bi_flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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__bi_local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a ^= mask;
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__bi_local_irq_restore(flags);
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return retval;
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}
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}
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/*
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* __test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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|
*/
|
|
static inline int __test_and_change_bit(unsigned long nr,
|
|
volatile unsigned long *addr)
|
|
{
|
|
volatile unsigned long *a = addr;
|
|
unsigned long mask;
|
|
int retval;
|
|
|
|
a += (nr >> SZLONG_LOG);
|
|
mask = 1UL << (nr & SZLONG_MASK);
|
|
retval = ((mask & *a) != 0);
|
|
*a ^= mask;
|
|
|
|
return retval;
|
|
}
|
|
|
|
#undef __bi_flags
|
|
#undef __bi_local_irq_save
|
|
#undef __bi_local_irq_restore
|
|
|
|
/*
|
|
* test_bit - Determine whether a bit is set
|
|
* @nr: bit number to test
|
|
* @addr: Address to start counting from
|
|
*/
|
|
static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
|
|
{
|
|
return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK));
|
|
}
|
|
|
|
/*
|
|
* ffz - find first zero in word.
|
|
* @word: The word to search
|
|
*
|
|
* Undefined if no zero exists, so code should check against ~0UL first.
|
|
*/
|
|
static inline unsigned long ffz(unsigned long word)
|
|
{
|
|
int b = 0, s;
|
|
|
|
word = ~word;
|
|
#ifdef CONFIG_MIPS32
|
|
s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
|
|
s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s;
|
|
s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s;
|
|
s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s;
|
|
s = 1; if (word << 31 != 0) s = 0; b += s;
|
|
#endif
|
|
#ifdef CONFIG_MIPS64
|
|
s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
|
|
s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s;
|
|
s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s;
|
|
s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s;
|
|
s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s;
|
|
s = 1; if (word << 63 != 0) s = 0; b += s;
|
|
#endif
|
|
|
|
return b;
|
|
}
|
|
|
|
/*
|
|
* __ffs - find first bit in word.
|
|
* @word: The word to search
|
|
*
|
|
* Undefined if no bit exists, so code should check against 0 first.
|
|
*/
|
|
static inline unsigned long __ffs(unsigned long word)
|
|
{
|
|
return ffz(~word);
|
|
}
|
|
|
|
/*
|
|
* fls: find last bit set.
|
|
*/
|
|
|
|
#define fls(x) generic_fls(x)
|
|
|
|
/*
|
|
* find_next_zero_bit - find the first zero bit in a memory region
|
|
* @addr: The address to base the search on
|
|
* @offset: The bitnumber to start searching at
|
|
* @size: The maximum size to search
|
|
*/
|
|
static inline unsigned long find_next_zero_bit(const unsigned long *addr,
|
|
unsigned long size, unsigned long offset)
|
|
{
|
|
const unsigned long *p = addr + (offset >> SZLONG_LOG);
|
|
unsigned long result = offset & ~SZLONG_MASK;
|
|
unsigned long tmp;
|
|
|
|
if (offset >= size)
|
|
return size;
|
|
size -= result;
|
|
offset &= SZLONG_MASK;
|
|
if (offset) {
|
|
tmp = *(p++);
|
|
tmp |= ~0UL >> (_MIPS_SZLONG-offset);
|
|
if (size < _MIPS_SZLONG)
|
|
goto found_first;
|
|
if (~tmp)
|
|
goto found_middle;
|
|
size -= _MIPS_SZLONG;
|
|
result += _MIPS_SZLONG;
|
|
}
|
|
while (size & ~SZLONG_MASK) {
|
|
if (~(tmp = *(p++)))
|
|
goto found_middle;
|
|
result += _MIPS_SZLONG;
|
|
size -= _MIPS_SZLONG;
|
|
}
|
|
if (!size)
|
|
return result;
|
|
tmp = *p;
|
|
|
|
found_first:
|
|
tmp |= ~0UL << size;
|
|
if (tmp == ~0UL) /* Are any bits zero? */
|
|
return result + size; /* Nope. */
|
|
found_middle:
|
|
return result + ffz(tmp);
|
|
}
|
|
|
|
#define find_first_zero_bit(addr, size) \
|
|
find_next_zero_bit((addr), (size), 0)
|
|
|
|
/*
|
|
* find_next_bit - find the next set bit in a memory region
|
|
* @addr: The address to base the search on
|
|
* @offset: The bitnumber to start searching at
|
|
* @size: The maximum size to search
|
|
*/
|
|
static inline unsigned long find_next_bit(const unsigned long *addr,
|
|
unsigned long size, unsigned long offset)
|
|
{
|
|
const unsigned long *p = addr + (offset >> SZLONG_LOG);
|
|
unsigned long result = offset & ~SZLONG_MASK;
|
|
unsigned long tmp;
|
|
|
|
if (offset >= size)
|
|
return size;
|
|
size -= result;
|
|
offset &= SZLONG_MASK;
|
|
if (offset) {
|
|
tmp = *(p++);
|
|
tmp &= ~0UL << offset;
|
|
if (size < _MIPS_SZLONG)
|
|
goto found_first;
|
|
if (tmp)
|
|
goto found_middle;
|
|
size -= _MIPS_SZLONG;
|
|
result += _MIPS_SZLONG;
|
|
}
|
|
while (size & ~SZLONG_MASK) {
|
|
if ((tmp = *(p++)))
|
|
goto found_middle;
|
|
result += _MIPS_SZLONG;
|
|
size -= _MIPS_SZLONG;
|
|
}
|
|
if (!size)
|
|
return result;
|
|
tmp = *p;
|
|
|
|
found_first:
|
|
tmp &= ~0UL >> (_MIPS_SZLONG - size);
|
|
if (tmp == 0UL) /* Are any bits set? */
|
|
return result + size; /* Nope. */
|
|
found_middle:
|
|
return result + __ffs(tmp);
|
|
}
|
|
|
|
/*
|
|
* find_first_bit - find the first set bit in a memory region
|
|
* @addr: The address to start the search at
|
|
* @size: The maximum size to search
|
|
*
|
|
* Returns the bit-number of the first set bit, not the number of the byte
|
|
* containing a bit.
|
|
*/
|
|
#define find_first_bit(addr, size) \
|
|
find_next_bit((addr), (size), 0)
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
/*
|
|
* Every architecture must define this function. It's the fastest
|
|
* way of searching a 140-bit bitmap where the first 100 bits are
|
|
* unlikely to be set. It's guaranteed that at least one of the 140
|
|
* bits is cleared.
|
|
*/
|
|
static inline int sched_find_first_bit(const unsigned long *b)
|
|
{
|
|
#ifdef CONFIG_MIPS32
|
|
if (unlikely(b[0]))
|
|
return __ffs(b[0]);
|
|
if (unlikely(b[1]))
|
|
return __ffs(b[1]) + 32;
|
|
if (unlikely(b[2]))
|
|
return __ffs(b[2]) + 64;
|
|
if (b[3])
|
|
return __ffs(b[3]) + 96;
|
|
return __ffs(b[4]) + 128;
|
|
#endif
|
|
#ifdef CONFIG_MIPS64
|
|
if (unlikely(b[0]))
|
|
return __ffs(b[0]);
|
|
if (unlikely(b[1]))
|
|
return __ffs(b[1]) + 64;
|
|
return __ffs(b[2]) + 128;
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* ffs - find first bit set
|
|
* @x: the word to search
|
|
*
|
|
* This is defined the same way as
|
|
* the libc and compiler builtin ffs routines, therefore
|
|
* differs in spirit from the above ffz (man ffs).
|
|
*/
|
|
|
|
#define ffs(x) generic_ffs(x)
|
|
|
|
/*
|
|
* hweightN - returns the hamming weight of a N-bit word
|
|
* @x: the word to weigh
|
|
*
|
|
* The Hamming Weight of a number is the total number of bits set in it.
|
|
*/
|
|
|
|
#define hweight64(x) generic_hweight64(x)
|
|
#define hweight32(x) generic_hweight32(x)
|
|
#define hweight16(x) generic_hweight16(x)
|
|
#define hweight8(x) generic_hweight8(x)
|
|
|
|
static inline int __test_and_set_le_bit(unsigned long nr, unsigned long *addr)
|
|
{
|
|
unsigned char *ADDR = (unsigned char *) addr;
|
|
int mask, retval;
|
|
|
|
ADDR += nr >> 3;
|
|
mask = 1 << (nr & 0x07);
|
|
retval = (mask & *ADDR) != 0;
|
|
*ADDR |= mask;
|
|
|
|
return retval;
|
|
}
|
|
|
|
static inline int __test_and_clear_le_bit(unsigned long nr, unsigned long *addr)
|
|
{
|
|
unsigned char *ADDR = (unsigned char *) addr;
|
|
int mask, retval;
|
|
|
|
ADDR += nr >> 3;
|
|
mask = 1 << (nr & 0x07);
|
|
retval = (mask & *ADDR) != 0;
|
|
*ADDR &= ~mask;
|
|
|
|
return retval;
|
|
}
|
|
|
|
static inline int test_le_bit(unsigned long nr, const unsigned long * addr)
|
|
{
|
|
const unsigned char *ADDR = (const unsigned char *) addr;
|
|
int mask;
|
|
|
|
ADDR += nr >> 3;
|
|
mask = 1 << (nr & 0x07);
|
|
|
|
return ((mask & *ADDR) != 0);
|
|
}
|
|
|
|
static inline unsigned long find_next_zero_le_bit(unsigned long *addr,
|
|
unsigned long size, unsigned long offset)
|
|
{
|
|
unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG);
|
|
unsigned long result = offset & ~SZLONG_MASK;
|
|
unsigned long tmp;
|
|
|
|
if (offset >= size)
|
|
return size;
|
|
size -= result;
|
|
offset &= SZLONG_MASK;
|
|
if (offset) {
|
|
tmp = cpu_to_lelongp(p++);
|
|
tmp |= ~0UL >> (_MIPS_SZLONG-offset); /* bug or feature ? */
|
|
if (size < _MIPS_SZLONG)
|
|
goto found_first;
|
|
if (~tmp)
|
|
goto found_middle;
|
|
size -= _MIPS_SZLONG;
|
|
result += _MIPS_SZLONG;
|
|
}
|
|
while (size & ~SZLONG_MASK) {
|
|
if (~(tmp = cpu_to_lelongp(p++)))
|
|
goto found_middle;
|
|
result += _MIPS_SZLONG;
|
|
size -= _MIPS_SZLONG;
|
|
}
|
|
if (!size)
|
|
return result;
|
|
tmp = cpu_to_lelongp(p);
|
|
|
|
found_first:
|
|
tmp |= ~0UL << size;
|
|
if (tmp == ~0UL) /* Are any bits zero? */
|
|
return result + size; /* Nope. */
|
|
|
|
found_middle:
|
|
return result + ffz(tmp);
|
|
}
|
|
|
|
#define find_first_zero_le_bit(addr, size) \
|
|
find_next_zero_le_bit((addr), (size), 0)
|
|
|
|
#define ext2_set_bit(nr,addr) \
|
|
__test_and_set_le_bit((nr),(unsigned long*)addr)
|
|
#define ext2_clear_bit(nr, addr) \
|
|
__test_and_clear_le_bit((nr),(unsigned long*)addr)
|
|
#define ext2_set_bit_atomic(lock, nr, addr) \
|
|
({ \
|
|
int ret; \
|
|
spin_lock(lock); \
|
|
ret = ext2_set_bit((nr), (addr)); \
|
|
spin_unlock(lock); \
|
|
ret; \
|
|
})
|
|
|
|
#define ext2_clear_bit_atomic(lock, nr, addr) \
|
|
({ \
|
|
int ret; \
|
|
spin_lock(lock); \
|
|
ret = ext2_clear_bit((nr), (addr)); \
|
|
spin_unlock(lock); \
|
|
ret; \
|
|
})
|
|
#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
|
|
#define ext2_find_first_zero_bit(addr, size) \
|
|
find_first_zero_le_bit((unsigned long*)addr, size)
|
|
#define ext2_find_next_zero_bit(addr, size, off) \
|
|
find_next_zero_le_bit((unsigned long*)addr, size, off)
|
|
|
|
/*
|
|
* Bitmap functions for the minix filesystem.
|
|
*
|
|
* FIXME: These assume that Minix uses the native byte/bitorder.
|
|
* This limits the Minix filesystem's value for data exchange very much.
|
|
*/
|
|
#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
|
|
#define minix_set_bit(nr,addr) set_bit(nr,addr)
|
|
#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
|
|
#define minix_test_bit(nr,addr) test_bit(nr,addr)
|
|
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* _ASM_BITOPS_H */
|