487 lines
14 KiB
C
487 lines
14 KiB
C
#ifndef _ASM_POWERPC_PROCESSOR_H
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#define _ASM_POWERPC_PROCESSOR_H
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/*
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* Copyright (C) 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/reg.h>
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#ifdef CONFIG_VSX
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#define TS_FPRWIDTH 2
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#ifdef __BIG_ENDIAN__
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#define TS_FPROFFSET 0
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#define TS_VSRLOWOFFSET 1
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#else
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#define TS_FPROFFSET 1
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#define TS_VSRLOWOFFSET 0
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#endif
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#else
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#define TS_FPRWIDTH 1
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#define TS_FPROFFSET 0
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#endif
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#ifdef CONFIG_PPC64
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/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
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#define PPR_PRIORITY 3
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#ifdef __ASSEMBLY__
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#define INIT_PPR (PPR_PRIORITY << 50)
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#else
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#define INIT_PPR ((u64)PPR_PRIORITY << 50)
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_PPC64 */
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/cache.h>
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#include <asm/hw_breakpoint.h>
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/* We do _not_ want to define new machine types at all, those must die
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* in favor of using the device-tree
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* -- BenH.
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*/
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/* PREP sub-platform types. Unused */
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#define _PREP_Motorola 0x01 /* motorola prep */
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#define _PREP_Firm 0x02 /* firmworks prep */
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#define _PREP_IBM 0x00 /* ibm prep */
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#define _PREP_Bull 0x03 /* bull prep */
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/* CHRP sub-platform types. These are arbitrary */
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#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
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#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
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#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
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#define _CHRP_briq 0x07 /* TotalImpact's briQ */
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#if defined(__KERNEL__) && defined(CONFIG_PPC32)
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extern int _chrp_type;
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#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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/* Macros for adjusting thread priority (hardware multi-threading) */
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#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
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#define HMT_low() asm volatile("or 1,1,1 # low priority")
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#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
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#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
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#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
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#define HMT_high() asm volatile("or 3,3,3 # high priority")
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#ifdef __KERNEL__
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struct task_struct;
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void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
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void release_thread(struct task_struct *);
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#ifdef CONFIG_PPC32
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#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
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#error User TASK_SIZE overlaps with KERNEL_START address
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#endif
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#define TASK_SIZE (CONFIG_TASK_SIZE)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
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#endif
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#ifdef CONFIG_PPC64
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/* 64-bit user address space is 46-bits (64TB user VM) */
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#define TASK_SIZE_USER64 (0x0000400000000000UL)
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/*
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* 32-bit user address space is 4GB - 1 page
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* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
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*/
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#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
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#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
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TASK_SIZE_USER32 : TASK_SIZE_USER64)
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#define TASK_SIZE TASK_SIZE_OF(current)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
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#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
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#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
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TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
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#endif
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#ifdef __powerpc64__
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#define STACK_TOP_USER64 TASK_SIZE_USER64
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#define STACK_TOP_USER32 TASK_SIZE_USER32
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#define STACK_TOP (is_32bit_task() ? \
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STACK_TOP_USER32 : STACK_TOP_USER64)
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#define STACK_TOP_MAX STACK_TOP_USER64
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#else /* __powerpc64__ */
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#define STACK_TOP TASK_SIZE
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#define STACK_TOP_MAX STACK_TOP
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#endif /* __powerpc64__ */
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
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#define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET]
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/* FP and VSX 0-31 register set */
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struct thread_fp_state {
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u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
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u64 fpscr; /* Floating point status */
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};
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/* Complete AltiVec register set including VSCR */
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struct thread_vr_state {
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vector128 vr[32] __attribute__((aligned(16)));
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vector128 vscr __attribute__((aligned(16)));
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};
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struct debug_reg {
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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/*
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* The following help to manage the use of Debug Control Registers
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* om the BookE platforms.
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*/
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uint32_t dbcr0;
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uint32_t dbcr1;
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#ifdef CONFIG_BOOKE
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uint32_t dbcr2;
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#endif
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/*
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* The stored value of the DBSR register will be the value at the
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* last debug interrupt. This register can only be read from the
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* user (will never be written to) and has value while helping to
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* describe the reason for the last debug trap. Torez
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*/
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uint32_t dbsr;
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/*
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* The following will contain addresses used by debug applications
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* to help trace and trap on particular address locations.
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* The bits in the Debug Control Registers above help define which
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* of the following registers will contain valid data and/or addresses.
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*/
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unsigned long iac1;
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unsigned long iac2;
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#if CONFIG_PPC_ADV_DEBUG_IACS > 2
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unsigned long iac3;
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unsigned long iac4;
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#endif
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unsigned long dac1;
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unsigned long dac2;
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#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
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unsigned long dvc1;
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unsigned long dvc2;
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#endif
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#endif
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};
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struct thread_struct {
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unsigned long ksp; /* Kernel stack pointer */
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#ifdef CONFIG_PPC64
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unsigned long ksp_vsid;
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#endif
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struct pt_regs *regs; /* Pointer to saved register state */
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mm_segment_t fs; /* for get_fs() validation */
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#ifdef CONFIG_BOOKE
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/* BookE base exception scratch space; align on cacheline */
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unsigned long normsave[8] ____cacheline_aligned;
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#endif
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#ifdef CONFIG_PPC32
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void *pgdir; /* root of page-table tree */
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unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
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#endif
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/* Debug Registers */
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struct debug_reg debug;
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struct thread_fp_state fp_state;
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struct thread_fp_state *fp_save_area;
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int fpexc_mode; /* floating-point exception mode */
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unsigned int align_ctl; /* alignment handling control */
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#ifdef CONFIG_PPC64
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unsigned long start_tb; /* Start purr when proc switched in */
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unsigned long accum_tb; /* Total accumulated purr for process */
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct perf_event *ptrace_bps[HBP_NUM];
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/*
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* Helps identify source of single-step exception and subsequent
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* hw-breakpoint enablement
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*/
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struct perf_event *last_hit_ubp;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#endif
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struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
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unsigned long trap_nr; /* last trap # on this thread */
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u8 load_fp;
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#ifdef CONFIG_ALTIVEC
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u8 load_vec;
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struct thread_vr_state vr_state;
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struct thread_vr_state *vr_save_area;
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unsigned long vrsave;
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int used_vr; /* set if process has used altivec */
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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/* VSR status */
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int used_vsr; /* set if process has used VSX */
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#endif /* CONFIG_VSX */
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#ifdef CONFIG_SPE
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unsigned long evr[32]; /* upper 32-bits of SPE regs */
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u64 acc; /* Accumulator */
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unsigned long spefscr; /* SPE & eFP status */
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unsigned long spefscr_last; /* SPEFSCR value on last prctl
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call or trap return */
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int used_spe; /* set if process has used spe */
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#endif /* CONFIG_SPE */
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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u64 tm_tfhar; /* Transaction fail handler addr */
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u64 tm_texasr; /* Transaction exception & summary */
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u64 tm_tfiar; /* Transaction fail instr address reg */
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struct pt_regs ckpt_regs; /* Checkpointed registers */
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unsigned long tm_tar;
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unsigned long tm_ppr;
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unsigned long tm_dscr;
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/*
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* Transactional FP and VSX 0-31 register set.
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* NOTE: the sense of these is the opposite of the integer ckpt_regs!
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*
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* When a transaction is active/signalled/scheduled etc., *regs is the
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* most recent set of/speculated GPRs with ckpt_regs being the older
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* checkpointed regs to which we roll back if transaction aborts.
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*
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* However, fpr[] is the checkpointed 'base state' of FP regs, and
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* transact_fpr[] is the new set of transactional values.
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* VRs work the same way.
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*/
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struct thread_fp_state transact_fp;
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struct thread_vr_state transact_vr;
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unsigned long transact_vrsave;
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
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void* kvm_shadow_vcpu; /* KVM internal data */
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#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
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#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
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struct kvm_vcpu *kvm_vcpu;
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#endif
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#ifdef CONFIG_PPC64
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unsigned long dscr;
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unsigned long fscr;
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/*
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* This member element dscr_inherit indicates that the process
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* has explicitly attempted and changed the DSCR register value
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* for itself. Hence kernel wont use the default CPU DSCR value
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* contained in the PACA structure anymore during process context
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* switch. Once this variable is set, this behaviour will also be
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* inherited to all the children of this process from that point
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* onwards.
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*/
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int dscr_inherit;
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unsigned long ppr; /* used to save/restore SMT priority */
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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unsigned long tar;
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unsigned long ebbrr;
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unsigned long ebbhr;
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unsigned long bescr;
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unsigned long siar;
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unsigned long sdar;
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unsigned long sier;
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unsigned long mmcr2;
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unsigned mmcr0;
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unsigned used_ebb;
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unsigned long lmrr;
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unsigned long lmser;
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#endif
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};
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#define ARCH_MIN_TASKALIGN 16
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#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
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#define INIT_SP_LIMIT \
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(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
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#ifdef CONFIG_SPE
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#define SPEFSCR_INIT \
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.spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
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.spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
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#else
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#define SPEFSCR_INIT
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#endif
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#ifdef CONFIG_PPC32
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#define INIT_THREAD { \
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.ksp = INIT_SP, \
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.ksp_limit = INIT_SP_LIMIT, \
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.fs = KERNEL_DS, \
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.pgdir = swapper_pg_dir, \
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.fpexc_mode = MSR_FE0 | MSR_FE1, \
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SPEFSCR_INIT \
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}
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#else
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#define INIT_THREAD { \
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.ksp = INIT_SP, \
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.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
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.fs = KERNEL_DS, \
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.fpexc_mode = 0, \
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.ppr = INIT_PPR, \
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.fscr = FSCR_TAR | FSCR_EBB \
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}
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#endif
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/*
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* Return saved PC of a blocked thread. For now, this is the "user" PC
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*/
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#define thread_saved_pc(tsk) \
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((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
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#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
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unsigned long get_wchan(struct task_struct *p);
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#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
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#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
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/* Get/set floating-point exception mode */
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#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
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#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
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extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
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extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
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#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
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#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
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extern int get_endian(struct task_struct *tsk, unsigned long adr);
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extern int set_endian(struct task_struct *tsk, unsigned int val);
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#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
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#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
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extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
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extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
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extern void load_fp_state(struct thread_fp_state *fp);
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extern void store_fp_state(struct thread_fp_state *fp);
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extern void load_vr_state(struct thread_vr_state *vr);
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extern void store_vr_state(struct thread_vr_state *vr);
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static inline unsigned int __unpack_fe01(unsigned long msr_bits)
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{
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return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
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}
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static inline unsigned long __pack_fe01(unsigned int fpmode)
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{
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return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
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}
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#ifdef CONFIG_PPC64
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#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
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#else
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#define cpu_relax() barrier()
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#endif
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#define cpu_relax_lowlatency() cpu_relax()
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/* Check that a certain kernel stack pointer is valid in task_struct p */
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int validate_sp(unsigned long sp, struct task_struct *p,
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unsigned long nbytes);
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/*
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* Prefetch macros.
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*/
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#define ARCH_HAS_PREFETCH
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#define ARCH_HAS_PREFETCHW
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void prefetch(const void *x)
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{
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if (unlikely(!x))
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return;
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__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
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}
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static inline void prefetchw(const void *x)
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{
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if (unlikely(!x))
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return;
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__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
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}
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#define spin_lock_prefetch(x) prefetchw(x)
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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#ifdef CONFIG_PPC64
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static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
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{
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if (is_32)
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return sp & 0x0ffffffffUL;
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return sp;
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}
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#else
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static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
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{
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return sp;
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}
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#endif
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extern unsigned long cpuidle_disable;
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enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
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extern int powersave_nap; /* set if nap mode can be used in idle loop */
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extern unsigned long power7_nap(int check_irq);
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extern unsigned long power7_sleep(void);
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extern unsigned long power7_winkle(void);
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extern unsigned long power9_idle_stop(unsigned long stop_level);
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extern void flush_instruction_cache(void);
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extern void hard_reset_now(void);
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extern void poweroff_now(void);
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extern int fix_alignment(struct pt_regs *);
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extern void cvt_fd(float *from, double *to);
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extern void cvt_df(double *from, float *to);
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extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
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#ifdef CONFIG_PPC64
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/*
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* We handle most unaligned accesses in hardware. On the other hand
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* unaligned DMA can be very expensive on some ppc64 IO chips (it does
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* powers of 2 writes until it reaches sufficient alignment).
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*
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* Based on this we disable the IP header alignment in network drivers.
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*/
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#define NET_IP_ALIGN 0
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PROCESSOR_H */
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