295 lines
7.3 KiB
C
295 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* AMD SoC Power Management Controller Driver
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*
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* Copyright (c) 2020, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/suspend.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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/* SMU communication registers */
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#define AMD_PMC_REGISTER_MESSAGE 0x538
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#define AMD_PMC_REGISTER_RESPONSE 0x980
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#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
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/* Base address of SMU for mapping physical address to virtual address */
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#define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
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#define AMD_PMC_SMU_INDEX_DATA 0xBC
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#define AMD_PMC_MAPPING_SIZE 0x01000
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#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
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#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
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#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
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#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
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#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
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/* SMU Response Codes */
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#define AMD_PMC_RESULT_OK 0x01
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#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
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#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
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#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
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#define AMD_PMC_RESULT_FAILED 0xFF
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/* List of supported CPU ids */
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#define AMD_CPU_ID_RV 0x15D0
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#define AMD_CPU_ID_RN 0x1630
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#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
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#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
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#define AMD_SMU_FW_VERSION 0x0
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#define PMC_MSG_DELAY_MIN_US 100
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#define RESPONSE_REGISTER_LOOP_MAX 200
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enum amd_pmc_def {
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MSG_TEST = 0x01,
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MSG_OS_HINT_PCO,
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MSG_OS_HINT_RN,
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};
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struct amd_pmc_dev {
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void __iomem *regbase;
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void __iomem *smu_base;
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u32 base_addr;
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u32 cpu_id;
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struct device *dev;
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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struct dentry *dbgfs_dir;
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#endif /* CONFIG_DEBUG_FS */
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};
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static struct amd_pmc_dev pmc;
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static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
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{
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return ioread32(dev->regbase + reg_offset);
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}
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static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
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{
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iowrite32(val, dev->regbase + reg_offset);
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}
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#ifdef CONFIG_DEBUG_FS
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static int smu_fw_info_show(struct seq_file *s, void *unused)
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{
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struct amd_pmc_dev *dev = s->private;
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u32 value;
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value = ioread32(dev->smu_base + AMD_SMU_FW_VERSION);
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seq_printf(s, "SMU FW Info: %x\n", value);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
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static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
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{
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debugfs_remove_recursive(dev->dbgfs_dir);
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}
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static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
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{
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dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
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debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
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&smu_fw_info_fops);
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}
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#else
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static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
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{
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}
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static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
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{
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u32 value;
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
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dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
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dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
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value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
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dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
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}
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static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)
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{
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int rc;
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u8 msg;
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u32 val;
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/* Wait until we get a valid response */
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rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
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val, val > 0, PMC_MSG_DELAY_MIN_US,
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PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
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if (rc) {
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dev_err(dev->dev, "failed to talk to SMU\n");
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return rc;
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}
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/* Write zero to response register */
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amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
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/* Write argument into response register */
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amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);
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/* Write message ID to message ID register */
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msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;
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amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
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return 0;
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}
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static int __maybe_unused amd_pmc_suspend(struct device *dev)
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{
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struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
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int rc;
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rc = amd_pmc_send_cmd(pdev, 1);
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if (rc)
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dev_err(pdev->dev, "suspend failed\n");
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amd_pmc_dump_registers(pdev);
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return 0;
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}
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static int __maybe_unused amd_pmc_resume(struct device *dev)
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{
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struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
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int rc;
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rc = amd_pmc_send_cmd(pdev, 0);
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if (rc)
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dev_err(pdev->dev, "resume failed\n");
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amd_pmc_dump_registers(pdev);
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return 0;
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}
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static const struct dev_pm_ops amd_pmc_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(amd_pmc_suspend, amd_pmc_resume)
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};
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static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
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{ }
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};
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static int amd_pmc_probe(struct platform_device *pdev)
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{
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struct amd_pmc_dev *dev = &pmc;
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struct pci_dev *rdev;
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u32 base_addr_lo;
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u32 base_addr_hi;
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u64 base_addr;
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int err;
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u32 val;
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dev->dev = &pdev->dev;
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rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
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pci_dev_put(rdev);
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return -ENODEV;
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}
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dev->cpu_id = rdev->device;
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err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
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if (err) {
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dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
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pci_dev_put(rdev);
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return pcibios_err_to_errno(err);
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}
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err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
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if (err) {
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pci_dev_put(rdev);
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return pcibios_err_to_errno(err);
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}
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base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
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err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
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if (err) {
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dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
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pci_dev_put(rdev);
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return pcibios_err_to_errno(err);
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}
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err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
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if (err) {
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pci_dev_put(rdev);
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return pcibios_err_to_errno(err);
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}
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base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
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pci_dev_put(rdev);
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base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
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dev->smu_base = devm_ioremap(dev->dev, base_addr, AMD_PMC_MAPPING_SIZE);
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if (!dev->smu_base)
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return -ENOMEM;
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dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
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AMD_PMC_MAPPING_SIZE);
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if (!dev->regbase)
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return -ENOMEM;
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amd_pmc_dump_registers(dev);
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platform_set_drvdata(pdev, dev);
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amd_pmc_dbgfs_register(dev);
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return 0;
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}
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static int amd_pmc_remove(struct platform_device *pdev)
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{
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struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
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amd_pmc_dbgfs_unregister(dev);
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return 0;
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}
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static const struct acpi_device_id amd_pmc_acpi_ids[] = {
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{"AMDI0005", 0},
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{"AMD0004", 0},
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
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static struct platform_driver amd_pmc_driver = {
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.driver = {
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.name = "amd_pmc",
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.acpi_match_table = amd_pmc_acpi_ids,
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.pm = &amd_pmc_pm_ops,
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},
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.probe = amd_pmc_probe,
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.remove = amd_pmc_remove,
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};
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module_platform_driver(amd_pmc_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("AMD PMC Driver");
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