345 lines
8.4 KiB
C
345 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2015, Linaro Ltd.
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*
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* SAW power controller driver
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/qcom_scm.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include "dt_idle_states.h"
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#define MAX_PMIC_DATA 2
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#define MAX_SEQ_DATA 64
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#define SPM_CTL_INDEX 0x7f
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#define SPM_CTL_INDEX_SHIFT 4
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#define SPM_CTL_EN BIT(0)
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enum pm_sleep_mode {
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PM_SLEEP_MODE_STBY,
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PM_SLEEP_MODE_RET,
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PM_SLEEP_MODE_SPC,
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PM_SLEEP_MODE_PC,
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PM_SLEEP_MODE_NR,
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};
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enum spm_reg {
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SPM_REG_CFG,
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SPM_REG_SPM_CTL,
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SPM_REG_DLY,
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SPM_REG_PMIC_DLY,
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SPM_REG_PMIC_DATA_0,
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SPM_REG_PMIC_DATA_1,
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SPM_REG_VCTL,
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SPM_REG_SEQ_ENTRY,
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SPM_REG_SPM_STS,
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SPM_REG_PMIC_STS,
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SPM_REG_NR,
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};
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struct spm_reg_data {
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const u8 *reg_offset;
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u32 spm_cfg;
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u32 spm_dly;
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u32 pmic_dly;
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u32 pmic_data[MAX_PMIC_DATA];
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u8 seq[MAX_SEQ_DATA];
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u8 start_index[PM_SLEEP_MODE_NR];
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};
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struct spm_driver_data {
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struct cpuidle_driver cpuidle_driver;
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void __iomem *reg_base;
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const struct spm_reg_data *reg_data;
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};
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static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8974, 8084 */
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static const struct spm_reg_data spm_reg_8974_8084_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
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0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
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0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x20,
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[SPM_REG_PMIC_DLY] = 0x24,
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[SPM_REG_PMIC_DATA_0] = 0x28,
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[SPM_REG_PMIC_DATA_1] = 0x2C,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8064 */
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static const struct spm_reg_data spm_reg_8064_cpu = {
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.reg_offset = spm_reg_offset_v1_1,
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.spm_cfg = 0x1F,
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.pmic_dly = 0x02020004,
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.pmic_data[0] = 0x0084009C,
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.pmic_data[1] = 0x00A4001C,
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.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
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0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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if (drv->reg_data->reg_offset[reg])
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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}
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/* Ensure a guaranteed write, before return */
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static inline void spm_register_write_sync(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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u32 ret;
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if (!drv->reg_data->reg_offset[reg])
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return;
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do {
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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ret = readl_relaxed(drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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if (ret == val)
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break;
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cpu_relax();
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} while (1);
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}
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static inline u32 spm_register_read(struct spm_driver_data *drv,
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enum spm_reg reg)
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{
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return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
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}
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static void spm_set_low_power_mode(struct spm_driver_data *drv,
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enum pm_sleep_mode mode)
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{
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u32 start_index;
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u32 ctl_val;
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start_index = drv->reg_data->start_index[mode];
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ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
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ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
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ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
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ctl_val |= SPM_CTL_EN;
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spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
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}
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static int qcom_pm_collapse(unsigned long int unused)
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{
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qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
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/*
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* Returns here only if there was a pending interrupt and we did not
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* power down as a result.
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*/
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return -1;
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}
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static int qcom_cpu_spc(struct spm_driver_data *drv)
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{
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int ret;
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
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ret = cpu_suspend(0, qcom_pm_collapse);
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/*
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* ARM common code executes WFI without calling into our driver and
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* if the SPM mode is not reset, then we may accidently power down the
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* cpu when we intended only to gate the cpu clock.
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* Ensure the state is set to standby before returning.
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*/
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
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return ret;
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}
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static int spm_enter_idle_state(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int idx)
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{
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struct spm_driver_data *data = container_of(drv, struct spm_driver_data,
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cpuidle_driver);
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return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data);
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}
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static struct cpuidle_driver qcom_spm_idle_driver = {
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.name = "qcom_spm",
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.owner = THIS_MODULE,
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.states[0] = {
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.enter = spm_enter_idle_state,
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.exit_latency = 1,
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.target_residency = 1,
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.power_usage = UINT_MAX,
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.name = "WFI",
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.desc = "ARM WFI",
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}
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};
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static const struct of_device_id qcom_idle_state_match[] = {
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{ .compatible = "qcom,idle-state-spc", .data = spm_enter_idle_state },
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{ },
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};
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static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu)
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{
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int ret;
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memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv));
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drv->cpumask = (struct cpumask *)cpumask_of(cpu);
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/* Parse idle states from device tree */
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ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1);
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if (ret <= 0)
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return ret ? : -ENODEV;
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/* We have atleast one power down mode */
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return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask);
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}
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static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
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int *spm_cpu)
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{
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struct spm_driver_data *drv = NULL;
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struct device_node *cpu_node, *saw_node;
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int cpu;
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bool found = 0;
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for_each_possible_cpu(cpu) {
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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continue;
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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found = (saw_node == pdev->dev.of_node);
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of_node_put(saw_node);
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of_node_put(cpu_node);
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if (found)
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break;
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}
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if (found) {
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
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if (drv)
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*spm_cpu = cpu;
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}
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return drv;
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}
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static const struct of_device_id spm_match_table[] = {
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{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
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.data = &spm_reg_8974_8084_cpu },
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{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
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.data = &spm_reg_8064_cpu },
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{ },
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};
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static int spm_dev_probe(struct platform_device *pdev)
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{
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struct spm_driver_data *drv;
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struct resource *res;
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const struct of_device_id *match_id;
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void __iomem *addr;
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int cpu, ret;
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if (!qcom_scm_is_available())
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return -EPROBE_DEFER;
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drv = spm_get_drv(pdev, &cpu);
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if (!drv)
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return -EINVAL;
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platform_set_drvdata(pdev, drv);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(drv->reg_base))
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return PTR_ERR(drv->reg_base);
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match_id = of_match_node(spm_match_table, pdev->dev.of_node);
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if (!match_id)
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return -ENODEV;
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drv->reg_data = match_id->data;
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ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu);
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if (ret)
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return ret;
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/* Write the SPM sequences first.. */
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addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
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__iowrite32_copy(addr, drv->reg_data->seq,
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ARRAY_SIZE(drv->reg_data->seq) / 4);
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/*
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* ..and then the control registers.
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* On some SoC if the control registers are written first and if the
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* CPU was held in reset, the reset signal could trigger the SPM state
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* machine, before the sequences are completely written.
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*/
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spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
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spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
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spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
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spm_register_write(drv, SPM_REG_PMIC_DATA_0,
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drv->reg_data->pmic_data[0]);
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spm_register_write(drv, SPM_REG_PMIC_DATA_1,
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drv->reg_data->pmic_data[1]);
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/* Set up Standby as the default low power mode */
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spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
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return cpuidle_register(&drv->cpuidle_driver, NULL);
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}
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static int spm_dev_remove(struct platform_device *pdev)
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{
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struct spm_driver_data *drv = platform_get_drvdata(pdev);
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cpuidle_unregister(&drv->cpuidle_driver);
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return 0;
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}
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static struct platform_driver spm_driver = {
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.probe = spm_dev_probe,
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.remove = spm_dev_remove,
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.driver = {
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.name = "saw",
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.of_match_table = spm_match_table,
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},
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};
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builtin_platform_driver(spm_driver);
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