601 lines
14 KiB
C
601 lines
14 KiB
C
/*
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* VIA AGPGART routines.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include "agp.h"
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static const struct pci_device_id agp_via_pci_table[];
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#define VIA_GARTCTRL 0x80
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#define VIA_APSIZE 0x84
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#define VIA_ATTBASE 0x88
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#define VIA_AGP3_GARTCTRL 0x90
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#define VIA_AGP3_APSIZE 0x94
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#define VIA_AGP3_ATTBASE 0x98
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#define VIA_AGPSEL 0xfd
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static int via_fetch_size(void)
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{
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int i;
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u8 temp;
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struct aper_size_info_8 *values;
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values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
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pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp);
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return 0;
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}
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static int via_configure(void)
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{
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u32 temp;
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struct aper_size_info_8 *current_size;
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current_size = A_SIZE_8(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
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current_size->size_value);
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/* address to map too */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* GART control register */
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pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
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/* attbase - aperture GATT base */
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pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
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(agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
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return 0;
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}
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static void via_cleanup(void)
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{
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struct aper_size_info_8 *previous_size;
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previous_size = A_SIZE_8(agp_bridge->previous_size);
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pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
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previous_size->size_value);
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/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
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* during reinitialization.
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*/
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}
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static void via_tlbflush(struct agp_memory *mem)
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{
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u32 temp;
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pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp);
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temp |= (1<<7);
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pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
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temp &= ~(1<<7);
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pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp);
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}
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static const struct aper_size_info_8 via_generic_sizes[9] =
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{
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{256, 65536, 6, 0},
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{128, 32768, 5, 128},
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{64, 16384, 4, 192},
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{32, 8192, 3, 224},
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{16, 4096, 2, 240},
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{8, 2048, 1, 248},
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{4, 1024, 0, 252},
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{2, 512, 0, 254},
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{1, 256, 0, 255}
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};
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static int via_fetch_size_agp3(void)
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{
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int i;
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u16 temp;
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struct aper_size_info_16 *values;
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values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
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pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
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temp &= 0xfff;
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int via_configure_agp3(void)
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{
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u32 temp;
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struct aper_size_info_16 *current_size;
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current_size = A_SIZE_16(agp_bridge->current_size);
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/* address to map too */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* attbase - aperture GATT base */
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pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
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agp_bridge->gatt_bus_addr & 0xfffff000);
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/* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch
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* translation table first.
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* 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the
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* graphics AGP aperture for the AGP3.0 port.
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*/
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pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7));
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return 0;
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}
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static void via_cleanup_agp3(void)
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{
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struct aper_size_info_16 *previous_size;
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previous_size = A_SIZE_16(agp_bridge->previous_size);
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pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
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}
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static void via_tlbflush_agp3(struct agp_memory *mem)
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{
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u32 temp;
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pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
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pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
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}
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static const struct agp_bridge_driver via_agp3_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = agp3_generic_sizes,
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.size_type = U8_APER_SIZE,
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.num_aperture_sizes = 10,
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.needs_scratch_page = true,
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.configure = via_configure_agp3,
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.fetch_size = via_fetch_size_agp3,
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.cleanup = via_cleanup_agp3,
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.tlb_flush = via_tlbflush_agp3,
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.mask_memory = agp_generic_mask_memory,
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.masks = NULL,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = agp_generic_insert_memory,
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.remove_memory = agp_generic_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static const struct agp_bridge_driver via_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = via_generic_sizes,
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.size_type = U8_APER_SIZE,
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.num_aperture_sizes = 9,
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.needs_scratch_page = true,
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.configure = via_configure,
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.fetch_size = via_fetch_size,
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.cleanup = via_cleanup,
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.tlb_flush = via_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = NULL,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = agp_generic_insert_memory,
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.remove_memory = agp_generic_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static struct agp_device_ids via_agp_device_ids[] __devinitdata =
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{
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{
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.device_id = PCI_DEVICE_ID_VIA_82C597_0,
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.chipset_name = "Apollo VP3",
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},
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{
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.device_id = PCI_DEVICE_ID_VIA_82C598_0,
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.chipset_name = "Apollo MVP3",
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},
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{
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.device_id = PCI_DEVICE_ID_VIA_8501_0,
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.chipset_name = "Apollo MVP4",
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},
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/* VT8601 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8601_0,
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.chipset_name = "Apollo ProMedia/PLE133Ta",
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},
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/* VT82C693A / VT28C694T */
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{
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.device_id = PCI_DEVICE_ID_VIA_82C691_0,
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.chipset_name = "Apollo Pro 133",
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},
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{
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.device_id = PCI_DEVICE_ID_VIA_8371_0,
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.chipset_name = "KX133",
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},
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/* VT8633 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8633_0,
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.chipset_name = "Pro 266",
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},
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{
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.device_id = PCI_DEVICE_ID_VIA_XN266,
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.chipset_name = "Apollo Pro266",
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},
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/* VT8361 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8361,
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.chipset_name = "KLE133",
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},
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/* VT8365 / VT8362 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8363_0,
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.chipset_name = "Twister-K/KT133x/KM133",
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},
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/* VT8753A */
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{
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.device_id = PCI_DEVICE_ID_VIA_8753_0,
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.chipset_name = "P4X266",
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},
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/* VT8366 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8367_0,
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.chipset_name = "KT266/KY266x/KT333",
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},
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/* VT8633 (for CuMine/ Celeron) */
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{
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.device_id = PCI_DEVICE_ID_VIA_8653_0,
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.chipset_name = "Pro266T",
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},
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/* KM266 / PM266 */
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{
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.device_id = PCI_DEVICE_ID_VIA_XM266,
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.chipset_name = "PM266/KM266",
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},
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/* CLE266 */
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{
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.device_id = PCI_DEVICE_ID_VIA_862X_0,
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.chipset_name = "CLE266",
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},
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{
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.device_id = PCI_DEVICE_ID_VIA_8377_0,
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.chipset_name = "KT400/KT400A/KT600",
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},
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/* VT8604 / VT8605 / VT8603
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* (Apollo Pro133A chipset with S3 Savage4) */
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{
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.device_id = PCI_DEVICE_ID_VIA_8605_0,
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.chipset_name = "ProSavage PM133/PL133/PN133"
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},
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/* P4M266x/P4N266 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8703_51_0,
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.chipset_name = "P4M266x/P4N266",
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},
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/* VT8754 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8754C_0,
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.chipset_name = "PT800",
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},
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/* P4X600 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8763_0,
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.chipset_name = "P4X600"
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},
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/* KM400 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8378_0,
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.chipset_name = "KM400/KM400A",
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},
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/* PT880 */
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{
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.device_id = PCI_DEVICE_ID_VIA_PT880,
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.chipset_name = "PT880",
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},
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/* PT880 Ultra */
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{
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.device_id = PCI_DEVICE_ID_VIA_PT880ULTRA,
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.chipset_name = "PT880 Ultra",
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},
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/* PT890 */
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{
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.device_id = PCI_DEVICE_ID_VIA_8783_0,
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.chipset_name = "PT890",
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},
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/* PM800/PN800/PM880/PN880 */
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{
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.device_id = PCI_DEVICE_ID_VIA_PX8X0_0,
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.chipset_name = "PM800/PN800/PM880/PN880",
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},
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/* KT880 */
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{
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.device_id = PCI_DEVICE_ID_VIA_3269_0,
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.chipset_name = "KT880",
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},
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/* KTxxx/Px8xx */
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{
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.device_id = PCI_DEVICE_ID_VIA_83_87XX_1,
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.chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx",
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},
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/* P4M800 */
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{
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.device_id = PCI_DEVICE_ID_VIA_3296_0,
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.chipset_name = "P4M800",
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},
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/* P4M800CE */
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{
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.device_id = PCI_DEVICE_ID_VIA_P4M800CE,
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.chipset_name = "VT3314",
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},
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/* VT3324 / CX700 */
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{
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.device_id = PCI_DEVICE_ID_VIA_VT3324,
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.chipset_name = "CX700",
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},
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/* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
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* architecture, the AGP resource and behavior are different from
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* the traditional AGP which resides only in chipset. AGP is used
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* by 3D driver which wasn't available for the VT3336 and VT3364
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* generation until now. Unfortunately, by testing, VT3364 works
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* but VT3336 doesn't. - explanation from via, just leave this as
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* as a placeholder to avoid future patches adding it back in.
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*/
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#if 0
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{
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.device_id = PCI_DEVICE_ID_VIA_VT3336,
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.chipset_name = "VT3336",
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},
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#endif
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/* P4M890 */
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{
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.device_id = PCI_DEVICE_ID_VIA_P4M890,
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.chipset_name = "P4M890",
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},
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/* P4M900 */
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{
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.device_id = PCI_DEVICE_ID_VIA_VT3364,
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.chipset_name = "P4M900",
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},
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{ }, /* dummy final entry, always present */
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};
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/*
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* VIA's AGP3 chipsets do magick to put the AGP bridge compliant
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* with the same standards version as the graphics card.
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*/
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static void check_via_agp3 (struct agp_bridge_data *bridge)
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{
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u8 reg;
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pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®);
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/* Check AGP 2.0 compatibility mode. */
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if ((reg & (1<<1))==0)
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bridge->driver = &via_agp3_driver;
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}
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static int __devinit agp_via_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_device_ids *devs = via_agp_device_ids;
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struct agp_bridge_data *bridge;
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int j = 0;
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u8 cap_ptr;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return -ENODEV;
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j = ent - agp_via_pci_table;
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printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->dev = pdev;
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bridge->capndx = cap_ptr;
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bridge->driver = &via_driver;
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/*
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* Garg, there are KT400s with KT266 IDs.
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*/
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if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
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/* Is there a KT400 subsystem ? */
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if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) {
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printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
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check_via_agp3(bridge);
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}
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}
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/* If this is an AGP3 bridge, check which mode its in and adjust. */
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get_agp_version(bridge);
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if (bridge->major_version >= 3)
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check_via_agp3(bridge);
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/* Fill in the mode register */
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pci_read_config_dword(pdev,
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bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
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pci_set_drvdata(pdev, bridge);
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return agp_add_bridge(bridge);
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}
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static void __devexit agp_via_remove(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
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agp_remove_bridge(bridge);
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agp_put_bridge(bridge);
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}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
pci_save_state (pdev);
|
|
pci_set_power_state (pdev, PCI_D3hot);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int agp_via_resume(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
pci_set_power_state (pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
|
|
if (bridge->driver == &via_agp3_driver)
|
|
return via_configure_agp3();
|
|
else if (bridge->driver == &via_driver)
|
|
return via_configure();
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
/* must be the same order as name table above */
|
|
static const struct pci_device_id agp_via_pci_table[] = {
|
|
#define ID(x) \
|
|
{ \
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8), \
|
|
.class_mask = ~0, \
|
|
.vendor = PCI_VENDOR_ID_VIA, \
|
|
.device = x, \
|
|
.subvendor = PCI_ANY_ID, \
|
|
.subdevice = PCI_ANY_ID, \
|
|
}
|
|
ID(PCI_DEVICE_ID_VIA_82C597_0),
|
|
ID(PCI_DEVICE_ID_VIA_82C598_0),
|
|
ID(PCI_DEVICE_ID_VIA_8501_0),
|
|
ID(PCI_DEVICE_ID_VIA_8601_0),
|
|
ID(PCI_DEVICE_ID_VIA_82C691_0),
|
|
ID(PCI_DEVICE_ID_VIA_8371_0),
|
|
ID(PCI_DEVICE_ID_VIA_8633_0),
|
|
ID(PCI_DEVICE_ID_VIA_XN266),
|
|
ID(PCI_DEVICE_ID_VIA_8361),
|
|
ID(PCI_DEVICE_ID_VIA_8363_0),
|
|
ID(PCI_DEVICE_ID_VIA_8753_0),
|
|
ID(PCI_DEVICE_ID_VIA_8367_0),
|
|
ID(PCI_DEVICE_ID_VIA_8653_0),
|
|
ID(PCI_DEVICE_ID_VIA_XM266),
|
|
ID(PCI_DEVICE_ID_VIA_862X_0),
|
|
ID(PCI_DEVICE_ID_VIA_8377_0),
|
|
ID(PCI_DEVICE_ID_VIA_8605_0),
|
|
ID(PCI_DEVICE_ID_VIA_8703_51_0),
|
|
ID(PCI_DEVICE_ID_VIA_8754C_0),
|
|
ID(PCI_DEVICE_ID_VIA_8763_0),
|
|
ID(PCI_DEVICE_ID_VIA_8378_0),
|
|
ID(PCI_DEVICE_ID_VIA_PT880),
|
|
ID(PCI_DEVICE_ID_VIA_PT880ULTRA),
|
|
ID(PCI_DEVICE_ID_VIA_8783_0),
|
|
ID(PCI_DEVICE_ID_VIA_PX8X0_0),
|
|
ID(PCI_DEVICE_ID_VIA_3269_0),
|
|
ID(PCI_DEVICE_ID_VIA_83_87XX_1),
|
|
ID(PCI_DEVICE_ID_VIA_3296_0),
|
|
ID(PCI_DEVICE_ID_VIA_P4M800CE),
|
|
ID(PCI_DEVICE_ID_VIA_VT3324),
|
|
ID(PCI_DEVICE_ID_VIA_P4M890),
|
|
ID(PCI_DEVICE_ID_VIA_VT3364),
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
|
|
|
|
|
|
static struct pci_driver agp_via_pci_driver = {
|
|
.name = "agpgart-via",
|
|
.id_table = agp_via_pci_table,
|
|
.probe = agp_via_probe,
|
|
.remove = agp_via_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = agp_via_suspend,
|
|
.resume = agp_via_resume,
|
|
#endif
|
|
};
|
|
|
|
|
|
static int __init agp_via_init(void)
|
|
{
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
return pci_register_driver(&agp_via_pci_driver);
|
|
}
|
|
|
|
static void __exit agp_via_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&agp_via_pci_driver);
|
|
}
|
|
|
|
module_init(agp_via_init);
|
|
module_exit(agp_via_cleanup);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
|