136 lines
2.8 KiB
C
136 lines
2.8 KiB
C
/*
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* PIKA Warp(tm) NAND flash specific routines
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*
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* Copyright (c) 2008 PIKA Technologies
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* Sean MacLennan <smaclennan@pikatech.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/ndfc.h>
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#include <linux/of.h>
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#include <asm/machdep.h>
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#ifdef CONFIG_MTD_NAND_NDFC
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#define CS_NAND_0 1 /* use chip select 1 for NAND device 0 */
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#define WARP_NAND_FLASH_REG_ADDR 0xD0000000UL
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#define WARP_NAND_FLASH_REG_SIZE 0x2000
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static struct resource warp_ndfc = {
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.start = WARP_NAND_FLASH_REG_ADDR,
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.end = WARP_NAND_FLASH_REG_ADDR + WARP_NAND_FLASH_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct mtd_partition nand_parts[] = {
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{
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.name = "kernel",
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.offset = 0,
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.size = 0x0200000
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},
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{
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.name = "root",
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.offset = 0x0200000,
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.size = 0x3E00000
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},
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{
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.name = "persistent",
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.offset = 0x4000000,
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.size = 0x4000000
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},
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{
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.name = "persistent1",
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.offset = 0x8000000,
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.size = 0x4000000
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},
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{
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.name = "persistent2",
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.offset = 0xC000000,
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.size = 0x4000000
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}
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};
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struct ndfc_controller_settings warp_ndfc_settings = {
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.ccr_settings = (NDFC_CCR_BS(CS_NAND_0) | NDFC_CCR_ARAC1),
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.ndfc_erpn = 0,
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};
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static struct ndfc_chip_settings warp_chip0_settings = {
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.bank_settings = 0x80002222,
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};
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struct platform_nand_ctrl warp_nand_ctrl = {
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.priv = &warp_ndfc_settings,
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};
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static struct platform_device warp_ndfc_device = {
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.name = "ndfc-nand",
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.id = 0,
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.dev = {
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.platform_data = &warp_nand_ctrl,
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},
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.num_resources = 1,
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.resource = &warp_ndfc,
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};
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/* Do NOT set the ecclayout: let it default so it is correct for both
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* 64M and 256M flash chips.
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*/
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static struct platform_nand_chip warp_nand_chip0 = {
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.nr_chips = 1,
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.chip_offset = CS_NAND_0,
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.nr_partitions = ARRAY_SIZE(nand_parts),
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.partitions = nand_parts,
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.chip_delay = 20,
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.priv = &warp_chip0_settings,
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};
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static struct platform_device warp_nand_device = {
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.name = "ndfc-chip",
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.id = 0,
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.num_resources = 0,
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.dev = {
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.platform_data = &warp_nand_chip0,
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.parent = &warp_ndfc_device.dev,
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}
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};
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static int warp_setup_nand_flash(void)
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{
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struct device_node *np;
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/* Try to detect a rev A based on NOR size. */
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np = of_find_compatible_node(NULL, NULL, "cfi-flash");
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if (np) {
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struct property *pp;
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pp = of_find_property(np, "reg", NULL);
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if (pp && (pp->length == 12)) {
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u32 *v = pp->value;
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if (v[2] == 0x4000000) {
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/* Rev A = 64M NAND */
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warp_nand_chip0.nr_partitions = 3;
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nand_parts[1].size = 0x3000000;
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nand_parts[2].offset = 0x3200000;
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nand_parts[2].size = 0x0e00000;
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}
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}
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of_node_put(np);
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}
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platform_device_register(&warp_ndfc_device);
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platform_device_register(&warp_nand_device);
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return 0;
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}
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machine_device_initcall(warp, warp_setup_nand_flash);
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#endif
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