435 lines
12 KiB
C
435 lines
12 KiB
C
/*
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* linux/arch/arm/mach-omap1/time.c
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*
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* OMAP Timers
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*
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* Copyright (C) 2004 Nokia Corporation
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* Partial timer rewrite and additional dynamic tick timer support by
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* Tony Lindgen <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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*
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* MPU timer code based on the older MPU timer code for OMAP
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/leds.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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struct sys_timer omap_timer;
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#ifdef CONFIG_OMAP_MPU_TIMER
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/*
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* ---------------------------------------------------------------------------
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* MPU timer
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* ---------------------------------------------------------------------------
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*/
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#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
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#define OMAP_MPU_TIMER_OFFSET 0x100
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/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
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* converted to use kHz by Kevin Hilman */
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/* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george at mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift.
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* -johnstul at us.ibm.com "math is hard, lets go shopping!"
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*/
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static unsigned long cyc2ns_scale;
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#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
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static inline void set_cyc2ns_scale(unsigned long cpu_khz)
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{
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cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
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}
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static inline unsigned long long cycles_2_ns(unsigned long long cyc)
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{
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return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
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}
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/*
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* MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
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* will break. On P2, the timer count rate is 6.5 MHz after programming PTV
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* with 0. This divides the 13MHz input by 2, and is undocumented.
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*/
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#ifdef CONFIG_MACH_OMAP_PERSEUS2
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/* REVISIT: This ifdef construct should be replaced by a query to clock
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* framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
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*/
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#define MPU_TICKS_PER_SEC (13000000 / 2)
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#else
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#define MPU_TICKS_PER_SEC (12000000 / 2)
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#endif
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#define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1)
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typedef struct {
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u32 cntl; /* CNTL_TIMER, R/W */
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u32 load_tim; /* LOAD_TIM, W */
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u32 read_tim; /* READ_TIM, R */
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} omap_mpu_timer_regs_t;
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#define omap_mpu_timer_base(n) \
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((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
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(n)*OMAP_MPU_TIMER_OFFSET))
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static inline unsigned long omap_mpu_timer_read(int nr)
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{
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volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
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return timer->read_tim;
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}
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static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
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{
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volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
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timer->cntl = MPU_TIMER_CLOCK_ENABLE;
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udelay(1);
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timer->load_tim = load_val;
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udelay(1);
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timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
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}
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unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
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{
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unsigned long long nsec;
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nsec = cycles_2_ns((unsigned long long)nr_ticks);
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return (unsigned long)nsec / 1000;
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}
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/*
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* Last processed system timer interrupt
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*/
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static unsigned long omap_mpu_timer_last = 0;
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/*
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* Returns elapsed usecs since last system timer interrupt
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*/
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static unsigned long omap_mpu_timer_gettimeoffset(void)
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{
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unsigned long now = 0 - omap_mpu_timer_read(0);
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unsigned long elapsed = now - omap_mpu_timer_last;
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return omap_mpu_timer_ticks_to_usecs(elapsed);
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}
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/*
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* Elapsed time between interrupts is calculated using timer0.
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* Latency during the interrupt is calculated using timer1.
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* Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
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*/
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static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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unsigned long now, latency;
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write_seqlock(&xtime_lock);
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now = 0 - omap_mpu_timer_read(0);
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latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
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omap_mpu_timer_last = now - latency;
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timer_tick(regs);
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction omap_mpu_timer_irq = {
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.name = "mpu timer",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = omap_mpu_timer_interrupt,
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};
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static unsigned long omap_mpu_timer1_overflows;
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static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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omap_mpu_timer1_overflows++;
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return IRQ_HANDLED;
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}
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static struct irqaction omap_mpu_timer1_irq = {
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.name = "mpu timer1 overflow",
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.flags = SA_INTERRUPT,
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.handler = omap_mpu_timer1_interrupt,
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};
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static __init void omap_init_mpu_timer(void)
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{
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set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
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omap_timer.offset = omap_mpu_timer_gettimeoffset;
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setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
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setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
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omap_mpu_timer_start(0, 0xffffffff);
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omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
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}
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long ticks = 0 - omap_mpu_timer_read(0);
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unsigned long long ticks64;
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ticks64 = omap_mpu_timer1_overflows;
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ticks64 <<= 32;
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ticks64 |= ticks;
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return cycles_2_ns(ticks64);
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}
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#endif /* CONFIG_OMAP_MPU_TIMER */
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#ifdef CONFIG_OMAP_32K_TIMER
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#ifdef CONFIG_ARCH_OMAP15XX
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#error OMAP 32KHz timer does not currently work on 15XX!
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#endif
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/*
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* ---------------------------------------------------------------------------
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* 32KHz OS timer
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*
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* This currently works only on 16xx, as 1510 does not have the continuous
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* 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
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* of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
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* on 1510 would be possible, but the timer would not be as accurate as
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* with the 32KHz synchronized timer.
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* ---------------------------------------------------------------------------
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*/
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#define OMAP_32K_TIMER_BASE 0xfffb9000
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#define OMAP_32K_TIMER_CR 0x08
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#define OMAP_32K_TIMER_TVR 0x00
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#define OMAP_32K_TIMER_TCR 0x04
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#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
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/*
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* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
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* so with HZ = 100, TVR = 327.68.
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*/
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#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
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#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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omap_writew(val, reg + OMAP_32K_TIMER_BASE);
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}
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static inline unsigned long omap_32k_timer_read(int reg)
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{
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return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
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}
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/*
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* The 32KHz synchronized timer is an additional timer on 16xx.
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* It is always running.
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*/
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static inline unsigned long omap_32k_sync_timer_read(void)
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{
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return omap_readl(TIMER_32K_SYNCHRONIZED);
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}
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
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omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
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}
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/*
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* Rounds down to nearest usec. Note that this will overflow for larger values.
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*/
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static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
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{
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return (ticks_32k * 5*5*5*5*5*5) >> 9;
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}
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/*
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* Rounds down to nearest nsec.
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*/
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static inline unsigned long long
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omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
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{
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return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
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}
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static unsigned long omap_32k_last_tick = 0;
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/*
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* Returns elapsed usecs since last 32k timer interrupt
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*/
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static unsigned long omap_32k_timer_gettimeoffset(void)
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{
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unsigned long now = omap_32k_sync_timer_read();
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return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
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}
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/*
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* Returns current time from boot in nsecs. It's OK for this to wrap
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* around for now, as it's just a relative time stamp.
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*/
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unsigned long long sched_clock(void)
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{
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return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
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}
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/*
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* Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
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* function is also called from other interrupts to remove latency
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* issues with dynamic tick. In the dynamic tick case, we need to lock
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* with irqsave.
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*/
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static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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unsigned long flags;
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unsigned long now;
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write_seqlock_irqsave(&xtime_lock, flags);
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now = omap_32k_sync_timer_read();
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while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
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omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
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timer_tick(regs);
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}
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/* Restart timer so we don't drift off due to modulo or dynamic tick.
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* By default we program the next timer to be continuous to avoid
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* latencies during high system load. During dynamic tick operation the
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* continuous timer can be overridden from pm_idle to be longer.
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*/
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omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
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write_sequnlock_irqrestore(&xtime_lock, flags);
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_NO_IDLE_HZ
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/*
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* Programs the next timer interrupt needed. Called when dynamic tick is
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* enabled, and to reprogram the ticks to skip from pm_idle. Note that
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* we can keep the timer continuous, and don't need to set it to run in
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* one-shot mode. This is because the timer will get reprogrammed again
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* after next interrupt.
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*/
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void omap_32k_timer_reprogram(unsigned long next_tick)
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{
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omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
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}
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static struct irqaction omap_32k_timer_irq;
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extern struct timer_update_handler timer_update;
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static int omap_32k_timer_enable_dyn_tick(void)
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{
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/* No need to reprogram timer, just use the next interrupt */
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return 0;
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}
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static int omap_32k_timer_disable_dyn_tick(void)
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{
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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return 0;
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}
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static struct dyn_tick_timer omap_dyn_tick_timer = {
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.enable = omap_32k_timer_enable_dyn_tick,
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.disable = omap_32k_timer_disable_dyn_tick,
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.reprogram = omap_32k_timer_reprogram,
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.handler = omap_32k_timer_interrupt,
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};
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#endif /* CONFIG_NO_IDLE_HZ */
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static struct irqaction omap_32k_timer_irq = {
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.name = "32KHz timer",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = omap_32k_timer_interrupt,
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};
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static __init void omap_init_32k_timer(void)
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{
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#ifdef CONFIG_NO_IDLE_HZ
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omap_timer.dyn_tick = &omap_dyn_tick_timer;
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#endif
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setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
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omap_timer.offset = omap_32k_timer_gettimeoffset;
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omap_32k_last_tick = omap_32k_sync_timer_read();
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omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
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}
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#endif /* CONFIG_OMAP_32K_TIMER */
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/*
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* ---------------------------------------------------------------------------
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* Timer initialization
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* ---------------------------------------------------------------------------
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*/
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static void __init omap_timer_init(void)
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{
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#if defined(CONFIG_OMAP_MPU_TIMER)
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omap_init_mpu_timer();
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#elif defined(CONFIG_OMAP_32K_TIMER)
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omap_init_32k_timer();
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#else
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#error No system timer selected in Kconfig!
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#endif
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}
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struct sys_timer omap_timer = {
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.init = omap_timer_init,
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.offset = NULL, /* Initialized later */
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};
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