158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
/*
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* Interrupt controller driver for Xilinx Virtex FPGAs
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*
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* Copyright (C) 2007 Secret Lab Technologies Ltd.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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/*
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* This is a driver for the interrupt controller typically found in
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* Xilinx Virtex FPGA designs.
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*
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* The interrupt sense levels are hard coded into the FPGA design with
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* typically a 1:1 relationship between irq lines and devices (no shared
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* irq lines). Therefore, this driver does not attempt to handle edge
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* and level interrupts differently.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/irq.h>
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/*
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* INTC Registers
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*/
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#define XINTC_ISR 0 /* Interrupt Status */
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#define XINTC_IPR 4 /* Interrupt Pending */
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#define XINTC_IER 8 /* Interrupt Enable */
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#define XINTC_IAR 12 /* Interrupt Acknowledge */
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#define XINTC_SIE 16 /* Set Interrupt Enable bits */
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#define XINTC_CIE 20 /* Clear Interrupt Enable bits */
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#define XINTC_IVR 24 /* Interrupt Vector */
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#define XINTC_MER 28 /* Master Enable */
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static struct irq_host *master_irqhost;
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/*
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* IRQ Chip operations
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*/
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static void xilinx_intc_mask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void * regs = get_irq_chip_data(virq);
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pr_debug("mask: %d\n", irq);
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out_be32(regs + XINTC_CIE, 1 << irq);
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}
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static void xilinx_intc_unmask(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void * regs = get_irq_chip_data(virq);
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pr_debug("unmask: %d\n", irq);
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out_be32(regs + XINTC_SIE, 1 << irq);
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}
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static void xilinx_intc_ack(unsigned int virq)
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{
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int irq = virq_to_hw(virq);
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void * regs = get_irq_chip_data(virq);
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pr_debug("ack: %d\n", irq);
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out_be32(regs + XINTC_IAR, 1 << irq);
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}
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static struct irq_chip xilinx_intc_irqchip = {
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.typename = "Xilinx INTC",
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.mask = xilinx_intc_mask,
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.unmask = xilinx_intc_unmask,
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.ack = xilinx_intc_ack,
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};
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/*
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* IRQ Host operations
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*/
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static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t irq)
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{
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set_irq_chip_data(virq, h->host_data);
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set_irq_chip_and_handler(virq, &xilinx_intc_irqchip, handle_level_irq);
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set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static struct irq_host_ops xilinx_intc_ops = {
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.map = xilinx_intc_map,
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};
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struct irq_host * __init
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xilinx_intc_init(struct device_node *np)
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{
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struct irq_host * irq;
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struct resource res;
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void * regs;
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int rc;
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/* Find and map the intc registers */
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rc = of_address_to_resource(np, 0, &res);
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if (rc) {
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printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n");
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return NULL;
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}
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regs = ioremap(res.start, 32);
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printk(KERN_INFO "Xilinx intc at 0x%08LX mapped to 0x%p\n",
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res.start, regs);
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/* Setup interrupt controller */
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out_be32(regs + XINTC_IER, 0); /* disable all irqs */
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out_be32(regs + XINTC_IAR, ~(u32) 0); /* Acknowledge pending irqs */
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out_be32(regs + XINTC_MER, 0x3UL); /* Turn on the Master Enable. */
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/* Allocate and initialize an irq_host structure. */
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irq = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, 32, &xilinx_intc_ops, -1);
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if (!irq)
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panic(__FILE__ ": Cannot allocate IRQ host\n");
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irq->host_data = regs;
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return irq;
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}
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int xilinx_intc_get_irq(void)
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{
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void * regs = master_irqhost->host_data;
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pr_debug("get_irq:\n");
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return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
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}
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void __init xilinx_intc_init_tree(void)
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{
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struct device_node *np;
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/* find top level interrupt controller */
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for_each_compatible_node(np, NULL, "xlnx,opb-intc-1.00.c") {
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if (!of_get_property(np, "interrupts", NULL))
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break;
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}
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if (!np) {
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for_each_compatible_node(np, NULL, "xlnx,xps-intc-1.00.a") {
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if (!of_get_property(np, "interrupts", NULL))
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break;
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}
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}
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/* xilinx interrupt controller needs to be top level */
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BUG_ON(!np);
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master_irqhost = xilinx_intc_init(np);
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BUG_ON(!master_irqhost);
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irq_set_default_host(master_irqhost);
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of_node_put(np);
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}
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