265 lines
7.8 KiB
C
265 lines
7.8 KiB
C
#ifndef _PPC64_PAGE_H
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#define _PPC64_PAGE_H
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/*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#ifdef __ASSEMBLY__
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#define ASM_CONST(x) x
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#else
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#define __ASM_CONST(x) x##UL
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#define ASM_CONST(x) __ASM_CONST(x)
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#endif
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/* PAGE_SHIFT determines the page size */
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#define SID_SHIFT 28
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#define SID_MASK 0xfffffffffUL
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#define ESID_MASK 0xfffffffff0000000UL
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#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
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#define HPAGE_SHIFT 24
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#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1))
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#ifdef CONFIG_HUGETLB_PAGE
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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/* For 64-bit processes the hugepage range is 1T-1.5T */
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#define TASK_HPAGE_BASE ASM_CONST(0x0000010000000000)
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#define TASK_HPAGE_END ASM_CONST(0x0000018000000000)
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#define LOW_ESID_MASK(addr, len) (((1U << (GET_ESID(addr+len-1)+1)) \
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- (1U << GET_ESID(addr))) & 0xffff)
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#define ARCH_HAS_HUGEPAGE_ONLY_RANGE
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#define ARCH_HAS_PREPARE_HUGEPAGE_RANGE
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#define touches_hugepage_low_range(mm, addr, len) \
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(LOW_ESID_MASK((addr), (len)) & mm->context.htlb_segs)
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#define touches_hugepage_high_range(addr, len) \
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(((addr) > (TASK_HPAGE_BASE-(len))) && ((addr) < TASK_HPAGE_END))
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#define __within_hugepage_low_range(addr, len, segmask) \
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((LOW_ESID_MASK((addr), (len)) | (segmask)) == (segmask))
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#define within_hugepage_low_range(addr, len) \
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__within_hugepage_low_range((addr), (len), \
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current->mm->context.htlb_segs)
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#define within_hugepage_high_range(addr, len) (((addr) >= TASK_HPAGE_BASE) \
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&& ((addr)+(len) <= TASK_HPAGE_END) && ((addr)+(len) >= (addr)))
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#define is_hugepage_only_range(mm, addr, len) \
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(touches_hugepage_high_range((addr), (len)) || \
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touches_hugepage_low_range((mm), (addr), (len)))
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#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
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#define in_hugepage_area(context, addr) \
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(cpu_has_feature(CPU_FTR_16M_PAGE) && \
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( (((addr) >= TASK_HPAGE_BASE) && ((addr) < TASK_HPAGE_END)) || \
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( ((addr) < 0x100000000L) && \
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((1 << GET_ESID(addr)) & (context).htlb_segs) ) ) )
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#else /* !CONFIG_HUGETLB_PAGE */
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#define in_hugepage_area(mm, addr) 0
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#endif /* !CONFIG_HUGETLB_PAGE */
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/* align addr on a size boundary - adjust address up/down if needed */
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#define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1)))
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#define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1)))
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/* align addr on a size boundary - adjust address up if needed */
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#define _ALIGN(addr,size) _ALIGN_UP(addr,size)
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/* to align the pointer to the (next) page boundary */
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#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE)
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/cache.h>
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#undef STRICT_MM_TYPECHECKS
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#define REGION_SIZE 4UL
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#define REGION_SHIFT 60UL
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#define REGION_MASK (((1UL<<REGION_SIZE)-1UL)<<REGION_SHIFT)
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static __inline__ void clear_page(void *addr)
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{
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unsigned long lines, line_size;
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line_size = ppc64_caches.dline_size;
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lines = ppc64_caches.dlines_per_page;
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__asm__ __volatile__(
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"mtctr %1 # clear_page\n\
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1: dcbz 0,%0\n\
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add %0,%0,%3\n\
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bdnz+ 1b"
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: "=r" (addr)
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: "r" (lines), "0" (addr), "r" (line_size)
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: "ctr", "memory");
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}
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extern void copy_page(void *to, void *from);
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struct page;
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extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
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extern void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *p);
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#ifdef STRICT_MM_TYPECHECKS
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/*
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* These are used to make use of C type-checking.
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* Entries in the pte table are 64b, while entries in the pgd & pmd are 32b.
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*/
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typedef struct { unsigned long pte; } pte_t;
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typedef struct { unsigned int pmd; } pmd_t;
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typedef struct { unsigned int pgd; } pgd_t;
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typedef struct { unsigned long pgprot; } pgprot_t;
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#define pte_val(x) ((x).pte)
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#define pmd_val(x) ((x).pmd)
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#define pgd_val(x) ((x).pgd)
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#define pgprot_val(x) ((x).pgprot)
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#define __pte(x) ((pte_t) { (x) } )
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#define __pmd(x) ((pmd_t) { (x) } )
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#define __pgd(x) ((pgd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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#else
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/*
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* .. while these make it easier on the compiler
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*/
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typedef unsigned long pte_t;
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typedef unsigned int pmd_t;
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typedef unsigned int pgd_t;
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typedef unsigned long pgprot_t;
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#define pte_val(x) (x)
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#define pmd_val(x) (x)
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#define pgd_val(x) (x)
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#define pgprot_val(x) (x)
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#define __pte(x) (x)
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#define __pmd(x) (x)
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#define __pgd(x) (x)
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#define __pgprot(x) (x)
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#endif
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/* Pure 2^n version of get_order */
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static inline int get_order(unsigned long size)
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{
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int order;
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size = (size-1) >> (PAGE_SHIFT-1);
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order = -1;
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do {
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size >>= 1;
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order++;
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} while (size);
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return order;
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}
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#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
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extern int page_is_ram(unsigned long pfn);
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extern u64 ppc64_pft_size; /* Log 2 of page table size */
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/* We do define AT_SYSINFO_EHDR but don't use the gate mecanism */
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#define __HAVE_ARCH_GATE_AREA 1
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#endif /* __ASSEMBLY__ */
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#ifdef MODULE
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#define __page_aligned __attribute__((__aligned__(PAGE_SIZE)))
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#else
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#define __page_aligned \
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__attribute__((__aligned__(PAGE_SIZE), \
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__section__(".data.page_aligned")))
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#endif
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/* This must match the -Ttext linker address */
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/* Note: tophys & tovirt make assumptions about how */
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/* KERNELBASE is defined for performance reasons. */
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/* When KERNELBASE moves, those macros may have */
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/* to change! */
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#define PAGE_OFFSET ASM_CONST(0xC000000000000000)
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#define KERNELBASE PAGE_OFFSET
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#define VMALLOCBASE ASM_CONST(0xD000000000000000)
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#define VMALLOC_REGION_ID (VMALLOCBASE >> REGION_SHIFT)
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#define KERNEL_REGION_ID (KERNELBASE >> REGION_SHIFT)
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#define USER_REGION_ID (0UL)
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#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
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#define __bpn_to_ba(x) ((((unsigned long)(x)) << PAGE_SHIFT) + KERNELBASE)
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#define __ba_to_bpn(x) ((((unsigned long)(x)) & ~REGION_MASK) >> PAGE_SHIFT)
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#define __va(x) ((void *)((unsigned long)(x) + KERNELBASE))
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#ifdef CONFIG_DISCONTIGMEM
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#define page_to_pfn(page) discontigmem_page_to_pfn(page)
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#define pfn_to_page(pfn) discontigmem_pfn_to_page(pfn)
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#define pfn_valid(pfn) discontigmem_pfn_valid(pfn)
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#endif
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#ifdef CONFIG_FLATMEM
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#define pfn_to_page(pfn) (mem_map + (pfn))
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#define page_to_pfn(page) ((unsigned long)((page) - mem_map))
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#define pfn_valid(pfn) ((pfn) < max_mapnr)
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#endif
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#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
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#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
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#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
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/*
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* Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
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* and needs to be executable. This means the whole heap ends
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* up being executable.
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*/
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#define VM_DATA_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_DATA_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_DATA_DEFAULT_FLAGS \
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(test_thread_flag(TIF_32BIT) ? \
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VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
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/*
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* This is the default if a program doesn't have a PT_GNU_STACK
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* program header entry. The PPC64 ELF ABI has a non executable stack
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* stack by default, so in the absense of a PT_GNU_STACK program header
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* we turn execute permission off.
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*/
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#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_STACK_DEFAULT_FLAGS \
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(test_thread_flag(TIF_32BIT) ? \
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VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
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#endif /* __KERNEL__ */
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#endif /* _PPC64_PAGE_H */
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