604 lines
16 KiB
C
604 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// ff-protocol-former.c - a part of driver for RME Fireface series
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//
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// Copyright (c) 2019 Takashi Sakamoto
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#include <linux/delay.h>
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#include "ff.h"
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#define FORMER_REG_SYNC_STATUS 0x0000801c0000ull
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/* For block write request. */
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#define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
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#define FORMER_REG_CLOCK_CONFIG 0x0000801c0004ull
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static int parse_clock_bits(u32 data, unsigned int *rate,
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enum snd_ff_clock_src *src)
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{
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static const struct {
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unsigned int rate;
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u32 mask;
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} *rate_entry, rate_entries[] = {
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{ 32000, 0x00000002, },
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{ 44100, 0x00000000, },
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{ 48000, 0x00000006, },
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{ 64000, 0x0000000a, },
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{ 88200, 0x00000008, },
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{ 96000, 0x0000000e, },
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{ 128000, 0x00000012, },
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{ 176400, 0x00000010, },
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{ 192000, 0x00000016, },
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};
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static const struct {
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enum snd_ff_clock_src src;
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u32 mask;
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} *clk_entry, clk_entries[] = {
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{ SND_FF_CLOCK_SRC_ADAT1, 0x00000000, },
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{ SND_FF_CLOCK_SRC_ADAT2, 0x00000400, },
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{ SND_FF_CLOCK_SRC_SPDIF, 0x00000c00, },
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{ SND_FF_CLOCK_SRC_WORD, 0x00001000, },
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{ SND_FF_CLOCK_SRC_LTC, 0x00001800, },
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
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rate_entry = rate_entries + i;
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if ((data & 0x0000001e) == rate_entry->mask) {
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*rate = rate_entry->rate;
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break;
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}
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}
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if (i == ARRAY_SIZE(rate_entries))
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return -EIO;
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if (data & 0x00000001) {
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*src = SND_FF_CLOCK_SRC_INTERNAL;
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} else {
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for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
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clk_entry = clk_entries + i;
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if ((data & 0x00001c00) == clk_entry->mask) {
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*src = clk_entry->src;
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break;
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}
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}
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if (i == ARRAY_SIZE(clk_entries))
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return -EIO;
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}
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return 0;
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}
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static int former_get_clock(struct snd_ff *ff, unsigned int *rate,
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enum snd_ff_clock_src *src)
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{
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__le32 reg;
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u32 data;
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int err;
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err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
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FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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data = le32_to_cpu(reg);
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return parse_clock_bits(data, rate, src);
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}
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static int former_switch_fetching_mode(struct snd_ff *ff, bool enable)
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{
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unsigned int count;
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__le32 *reg;
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int i;
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int err;
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count = 0;
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for (i = 0; i < SND_FF_STREAM_MODE_COUNT; ++i)
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count = max(count, ff->spec->pcm_playback_channels[i]);
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reg = kcalloc(count, sizeof(__le32), GFP_KERNEL);
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if (!reg)
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return -ENOMEM;
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if (!enable) {
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/*
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* Each quadlet is corresponding to data channels in a data
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* blocks in reverse order. Precisely, quadlets for available
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* data channels should be enabled. Here, I take second best
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* to fetch PCM frames from all of data channels regardless of
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* stf.
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*/
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for (i = 0; i < count; ++i)
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reg[i] = cpu_to_le32(0x00000001);
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}
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_BLOCK_REQUEST,
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FORMER_REG_FETCH_PCM_FRAMES, reg,
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sizeof(__le32) * count, 0);
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kfree(reg);
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return err;
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}
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static void dump_clock_config(struct snd_ff *ff, struct snd_info_buffer *buffer)
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{
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__le32 reg;
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u32 data;
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unsigned int rate;
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enum snd_ff_clock_src src;
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const char *label;
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int err;
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err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
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FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0);
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if (err < 0)
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return;
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data = le32_to_cpu(reg);
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snd_iprintf(buffer, "Output S/PDIF format: %s (Emphasis: %s)\n",
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(data & 0x00000020) ? "Professional" : "Consumer",
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(data & 0x00000040) ? "on" : "off");
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snd_iprintf(buffer, "Optical output interface format: %s\n",
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(data & 0x00000100) ? "S/PDIF" : "ADAT");
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snd_iprintf(buffer, "Word output single speed: %s\n",
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(data & 0x00002000) ? "on" : "off");
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snd_iprintf(buffer, "S/PDIF input interface: %s\n",
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(data & 0x00000200) ? "Optical" : "Coaxial");
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err = parse_clock_bits(data, &rate, &src);
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if (err < 0)
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return;
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label = snd_ff_proc_get_clk_label(src);
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if (!label)
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return;
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snd_iprintf(buffer, "Clock configuration: %d %s\n", rate, label);
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}
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static void dump_sync_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
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{
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static const struct {
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char *const label;
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u32 locked_mask;
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u32 synced_mask;
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} *clk_entry, clk_entries[] = {
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{ "WDClk", 0x40000000, 0x20000000, },
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{ "S/PDIF", 0x00080000, 0x00040000, },
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{ "ADAT1", 0x00000400, 0x00001000, },
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{ "ADAT2", 0x00000800, 0x00002000, },
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};
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static const struct {
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char *const label;
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u32 mask;
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} *referred_entry, referred_entries[] = {
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{ "ADAT1", 0x00000000, },
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{ "ADAT2", 0x00400000, },
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{ "S/PDIF", 0x00c00000, },
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{ "WDclk", 0x01000000, },
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{ "TCO", 0x01400000, },
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};
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static const struct {
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unsigned int rate;
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u32 mask;
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} *rate_entry, rate_entries[] = {
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{ 32000, 0x02000000, },
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{ 44100, 0x04000000, },
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{ 48000, 0x06000000, },
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{ 64000, 0x08000000, },
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{ 88200, 0x0a000000, },
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{ 96000, 0x0c000000, },
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{ 128000, 0x0e000000, },
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{ 176400, 0x10000000, },
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{ 192000, 0x12000000, },
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};
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__le32 reg[2];
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u32 data[2];
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int i;
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int err;
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err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
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FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0);
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if (err < 0)
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return;
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data[0] = le32_to_cpu(reg[0]);
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data[1] = le32_to_cpu(reg[1]);
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snd_iprintf(buffer, "External source detection:\n");
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for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
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const char *state;
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clk_entry = clk_entries + i;
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if (data[0] & clk_entry->locked_mask) {
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if (data[0] & clk_entry->synced_mask)
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state = "sync";
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else
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state = "lock";
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} else {
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state = "none";
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}
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snd_iprintf(buffer, "%s: %s\n", clk_entry->label, state);
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}
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snd_iprintf(buffer, "Referred clock:\n");
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if (data[1] & 0x00000001) {
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snd_iprintf(buffer, "Internal\n");
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} else {
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unsigned int rate;
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const char *label;
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for (i = 0; i < ARRAY_SIZE(referred_entries); ++i) {
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referred_entry = referred_entries + i;
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if ((data[0] & 0x1e0000) == referred_entry->mask) {
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label = referred_entry->label;
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break;
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}
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}
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if (i == ARRAY_SIZE(referred_entries))
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label = "none";
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for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
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rate_entry = rate_entries + i;
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if ((data[0] & 0x1e000000) == rate_entry->mask) {
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rate = rate_entry->rate;
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break;
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}
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}
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if (i == ARRAY_SIZE(rate_entries))
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rate = 0;
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snd_iprintf(buffer, "%s %d\n", label, rate);
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}
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}
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static void former_dump_status(struct snd_ff *ff,
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struct snd_info_buffer *buffer)
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{
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dump_clock_config(ff, buffer);
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dump_sync_status(ff, buffer);
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}
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static int former_fill_midi_msg(struct snd_ff *ff,
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struct snd_rawmidi_substream *substream,
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unsigned int port)
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{
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u8 *buf = (u8 *)ff->msg_buf[port];
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int len;
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int i;
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len = snd_rawmidi_transmit_peek(substream, buf,
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SND_FF_MAXIMIM_MIDI_QUADS);
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if (len <= 0)
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return len;
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// One quadlet includes one byte.
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for (i = len - 1; i >= 0; --i)
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ff->msg_buf[port][i] = cpu_to_le32(buf[i]);
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ff->rx_bytes[port] = len;
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return len;
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}
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#define FF800_STF 0x0000fc88f000
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#define FF800_RX_PACKET_FORMAT 0x0000fc88f004
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#define FF800_ALLOC_TX_STREAM 0x0000fc88f008
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#define FF800_ISOC_COMM_START 0x0000fc88f00c
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#define FF800_TX_S800_FLAG 0x00000800
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#define FF800_ISOC_COMM_STOP 0x0000fc88f010
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#define FF800_TX_PACKET_ISOC_CH 0x0000801c0008
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static int allocate_tx_resources(struct snd_ff *ff)
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{
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__le32 reg;
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unsigned int count;
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unsigned int tx_isoc_channel;
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int err;
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reg = cpu_to_le32(ff->tx_stream.data_block_quadlets);
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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FF800_ALLOC_TX_STREAM, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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// Wait till the format of tx packet is available.
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count = 0;
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while (count++ < 10) {
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u32 data;
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err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
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FF800_TX_PACKET_ISOC_CH, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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data = le32_to_cpu(reg);
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if (data != 0xffffffff) {
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tx_isoc_channel = data;
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break;
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}
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msleep(50);
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}
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if (count >= 10)
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return -ETIMEDOUT;
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// NOTE: this is a makeshift to start OHCI 1394 IR context in the
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// channel. On the other hand, 'struct fw_iso_resources.allocated' is
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// not true and it's not deallocated at stop.
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ff->tx_resources.channel = tx_isoc_channel;
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return 0;
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}
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static int ff800_allocate_resources(struct snd_ff *ff, unsigned int rate)
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{
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u32 data;
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__le32 reg;
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int err;
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reg = cpu_to_le32(rate);
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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FF800_STF, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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// If starting isochronous communication immediately, change of STF has
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// no effect. In this case, the communication runs based on former STF.
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// Let's sleep for a bit.
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msleep(100);
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// Controllers should allocate isochronous resources for rx stream.
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err = fw_iso_resources_allocate(&ff->rx_resources,
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amdtp_stream_get_max_payload(&ff->rx_stream),
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fw_parent_device(ff->unit)->max_speed);
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if (err < 0)
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return err;
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// Set isochronous channel and the number of quadlets of rx packets.
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// This should be done before the allocation of tx resources to avoid
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// periodical noise.
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data = ff->rx_stream.data_block_quadlets << 3;
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data = (data << 8) | ff->rx_resources.channel;
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reg = cpu_to_le32(data);
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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FF800_RX_PACKET_FORMAT, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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return allocate_tx_resources(ff);
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}
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static int ff800_begin_session(struct snd_ff *ff, unsigned int rate)
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{
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unsigned int generation = ff->rx_resources.generation;
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__le32 reg;
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if (generation != fw_parent_device(ff->unit)->card->generation) {
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int err = fw_iso_resources_update(&ff->rx_resources);
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if (err < 0)
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return err;
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}
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reg = cpu_to_le32(0x80000000);
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reg |= cpu_to_le32(ff->tx_stream.data_block_quadlets);
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if (fw_parent_device(ff->unit)->max_speed == SCODE_800)
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reg |= cpu_to_le32(FF800_TX_S800_FLAG);
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return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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FF800_ISOC_COMM_START, ®, sizeof(reg), 0);
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}
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static void ff800_finish_session(struct snd_ff *ff)
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{
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__le32 reg;
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reg = cpu_to_le32(0x80000000);
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snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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FF800_ISOC_COMM_STOP, ®, sizeof(reg), 0);
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}
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// Fireface 800 doesn't allow drivers to register lower 4 bytes of destination
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// address.
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// A write transaction to clear registered higher 4 bytes of destination address
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// has an effect to suppress asynchronous transaction from device.
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static void ff800_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
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__le32 *buf, size_t length)
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{
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int i;
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for (i = 0; i < length / 4; i++) {
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u8 byte = le32_to_cpu(buf[i]) & 0xff;
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struct snd_rawmidi_substream *substream;
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substream = READ_ONCE(ff->tx_midi_substreams[0]);
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if (substream)
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snd_rawmidi_receive(substream, &byte, 1);
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}
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}
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const struct snd_ff_protocol snd_ff_protocol_ff800 = {
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.handle_midi_msg = ff800_handle_midi_msg,
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.fill_midi_msg = former_fill_midi_msg,
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.get_clock = former_get_clock,
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.switch_fetching_mode = former_switch_fetching_mode,
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.allocate_resources = ff800_allocate_resources,
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.begin_session = ff800_begin_session,
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.finish_session = ff800_finish_session,
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.dump_status = former_dump_status,
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};
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#define FF400_STF 0x000080100500ull
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#define FF400_RX_PACKET_FORMAT 0x000080100504ull
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#define FF400_ISOC_COMM_START 0x000080100508ull
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#define FF400_TX_PACKET_FORMAT 0x00008010050cull
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#define FF400_ISOC_COMM_STOP 0x000080100510ull
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// Fireface 400 manages isochronous channel number in 3 bit field. Therefore,
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// we can allocate between 0 and 7 channel.
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static int ff400_allocate_resources(struct snd_ff *ff, unsigned int rate)
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{
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__le32 reg;
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enum snd_ff_stream_mode mode;
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int i;
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int err;
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// Check whether the given value is supported or not.
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for (i = 0; i < CIP_SFC_COUNT; i++) {
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if (amdtp_rate_table[i] == rate)
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break;
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}
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if (i >= CIP_SFC_COUNT)
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return -EINVAL;
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// Set the number of data blocks transferred in a second.
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reg = cpu_to_le32(rate);
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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FF400_STF, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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msleep(100);
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err = snd_ff_stream_get_multiplier_mode(i, &mode);
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if (err < 0)
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return err;
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// Keep resources for in-stream.
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ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
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err = fw_iso_resources_allocate(&ff->tx_resources,
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amdtp_stream_get_max_payload(&ff->tx_stream),
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fw_parent_device(ff->unit)->max_speed);
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if (err < 0)
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return err;
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// Keep resources for out-stream.
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ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
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err = fw_iso_resources_allocate(&ff->rx_resources,
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amdtp_stream_get_max_payload(&ff->rx_stream),
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fw_parent_device(ff->unit)->max_speed);
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if (err < 0)
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fw_iso_resources_free(&ff->tx_resources);
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return err;
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}
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static int ff400_begin_session(struct snd_ff *ff, unsigned int rate)
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{
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unsigned int generation = ff->rx_resources.generation;
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__le32 reg;
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int err;
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if (generation != fw_parent_device(ff->unit)->card->generation) {
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err = fw_iso_resources_update(&ff->tx_resources);
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if (err < 0)
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return err;
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err = fw_iso_resources_update(&ff->rx_resources);
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if (err < 0)
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return err;
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}
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|
// Set isochronous channel and the number of quadlets of received
|
|
// packets.
|
|
reg = cpu_to_le32(((ff->rx_stream.data_block_quadlets << 3) << 8) |
|
|
ff->rx_resources.channel);
|
|
err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
|
|
FF400_RX_PACKET_FORMAT, ®, sizeof(reg), 0);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
// Set isochronous channel and the number of quadlets of transmitted
|
|
// packet.
|
|
// TODO: investigate the purpose of this 0x80.
|
|
reg = cpu_to_le32((0x80 << 24) |
|
|
(ff->tx_resources.channel << 5) |
|
|
(ff->tx_stream.data_block_quadlets));
|
|
err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
|
|
FF400_TX_PACKET_FORMAT, ®, sizeof(reg), 0);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
// Allow to transmit packets.
|
|
reg = cpu_to_le32(0x00000001);
|
|
return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
|
|
FF400_ISOC_COMM_START, ®, sizeof(reg), 0);
|
|
}
|
|
|
|
static void ff400_finish_session(struct snd_ff *ff)
|
|
{
|
|
__le32 reg;
|
|
|
|
reg = cpu_to_le32(0x80000000);
|
|
snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
|
|
FF400_ISOC_COMM_STOP, ®, sizeof(reg), 0);
|
|
}
|
|
|
|
// For Fireface 400, lower 4 bytes of destination address is configured by bit
|
|
// flag in quadlet register (little endian) at 0x'0000'801'0051c. Drivers can
|
|
// select one of 4 options:
|
|
//
|
|
// bit flags: offset of destination address
|
|
// - 0x04000000: 0x'....'....'0000'0000
|
|
// - 0x08000000: 0x'....'....'0000'0080
|
|
// - 0x10000000: 0x'....'....'0000'0100
|
|
// - 0x20000000: 0x'....'....'0000'0180
|
|
//
|
|
// Drivers can suppress the device to transfer asynchronous transactions by
|
|
// using below 2 bits.
|
|
// - 0x01000000: suppress transmission
|
|
// - 0x02000000: suppress transmission
|
|
//
|
|
// Actually, the register is write-only and includes the other options such as
|
|
// input attenuation. This driver allocates destination address with '0000'0000
|
|
// in its lower offset and expects userspace application to configure the
|
|
// register for it.
|
|
static void ff400_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
|
|
__le32 *buf, size_t length)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < length / 4; i++) {
|
|
u32 quad = le32_to_cpu(buf[i]);
|
|
u8 byte;
|
|
unsigned int index;
|
|
struct snd_rawmidi_substream *substream;
|
|
|
|
/* Message in first port. */
|
|
/*
|
|
* This value may represent the index of this unit when the same
|
|
* units are on the same IEEE 1394 bus. This driver doesn't use
|
|
* it.
|
|
*/
|
|
index = (quad >> 8) & 0xff;
|
|
if (index > 0) {
|
|
substream = READ_ONCE(ff->tx_midi_substreams[0]);
|
|
if (substream != NULL) {
|
|
byte = quad & 0xff;
|
|
snd_rawmidi_receive(substream, &byte, 1);
|
|
}
|
|
}
|
|
|
|
/* Message in second port. */
|
|
index = (quad >> 24) & 0xff;
|
|
if (index > 0) {
|
|
substream = READ_ONCE(ff->tx_midi_substreams[1]);
|
|
if (substream != NULL) {
|
|
byte = (quad >> 16) & 0xff;
|
|
snd_rawmidi_receive(substream, &byte, 1);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
const struct snd_ff_protocol snd_ff_protocol_ff400 = {
|
|
.handle_midi_msg = ff400_handle_midi_msg,
|
|
.fill_midi_msg = former_fill_midi_msg,
|
|
.get_clock = former_get_clock,
|
|
.switch_fetching_mode = former_switch_fetching_mode,
|
|
.allocate_resources = ff400_allocate_resources,
|
|
.begin_session = ff400_begin_session,
|
|
.finish_session = ff400_finish_session,
|
|
.dump_status = former_dump_status,
|
|
};
|