181 lines
5.7 KiB
C
181 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Implement the default iomap interfaces
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*
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* (C) Copyright 2004 Linus Torvalds
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*/
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#ifdef CONFIG_PCI
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/**
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* pci_iomap_range - create a virtual mapping cookie for a PCI BAR
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* @dev: PCI device that owns the BAR
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* @bar: BAR number
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* @offset: map memory at the given offset in BAR
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* @maxlen: max length of the memory to map
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*
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* Using this function you will get a __iomem address to your device BAR.
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* You can access it using ioread*() and iowrite*(). These functions hide
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* the details if this is a MMIO or PIO address space and will just do what
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* you expect from them in the correct way.
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*
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* @maxlen specifies the maximum length to map. If you want to get access to
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* the complete BAR from offset to the end, pass %0 here.
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* */
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void __iomem *pci_iomap_range(struct pci_dev *dev,
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int bar,
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unsigned long offset,
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unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (len <= offset || !start)
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return NULL;
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len -= offset;
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start += offset;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return __pci_ioport_map(dev, start, len);
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if (flags & IORESOURCE_MEM)
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return ioremap(start, len);
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/* What? */
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return NULL;
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}
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EXPORT_SYMBOL(pci_iomap_range);
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/**
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* pci_iomap_wc_range - create a virtual WC mapping cookie for a PCI BAR
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* @dev: PCI device that owns the BAR
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* @bar: BAR number
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* @offset: map memory at the given offset in BAR
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* @maxlen: max length of the memory to map
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*
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* Using this function you will get a __iomem address to your device BAR.
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* You can access it using ioread*() and iowrite*(). These functions hide
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* the details if this is a MMIO or PIO address space and will just do what
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* you expect from them in the correct way. When possible write combining
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* is used.
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*
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* @maxlen specifies the maximum length to map. If you want to get access to
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* the complete BAR from offset to the end, pass %0 here.
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* */
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void __iomem *pci_iomap_wc_range(struct pci_dev *dev,
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int bar,
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unsigned long offset,
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unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (flags & IORESOURCE_IO)
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return NULL;
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if (len <= offset || !start)
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return NULL;
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len -= offset;
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start += offset;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_MEM)
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return ioremap_wc(start, len);
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/* What? */
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return NULL;
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}
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EXPORT_SYMBOL_GPL(pci_iomap_wc_range);
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/**
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* pci_iomap - create a virtual mapping cookie for a PCI BAR
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* @dev: PCI device that owns the BAR
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* @bar: BAR number
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* @maxlen: length of the memory to map
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*
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* Using this function you will get a __iomem address to your device BAR.
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* You can access it using ioread*() and iowrite*(). These functions hide
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* the details if this is a MMIO or PIO address space and will just do what
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* you expect from them in the correct way.
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*
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* @maxlen specifies the maximum length to map. If you want to get access to
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* the complete BAR without checking for its length first, pass %0 here.
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* */
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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return pci_iomap_range(dev, bar, 0, maxlen);
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}
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EXPORT_SYMBOL(pci_iomap);
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/**
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* pci_iomap_wc - create a virtual WC mapping cookie for a PCI BAR
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* @dev: PCI device that owns the BAR
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* @bar: BAR number
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* @maxlen: length of the memory to map
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*
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* Using this function you will get a __iomem address to your device BAR.
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* You can access it using ioread*() and iowrite*(). These functions hide
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* the details if this is a MMIO or PIO address space and will just do what
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* you expect from them in the correct way. When possible write combining
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* is used.
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*
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* @maxlen specifies the maximum length to map. If you want to get access to
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* the complete BAR without checking for its length first, pass %0 here.
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* */
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void __iomem *pci_iomap_wc(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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return pci_iomap_wc_range(dev, bar, 0, maxlen);
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}
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EXPORT_SYMBOL_GPL(pci_iomap_wc);
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/*
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* pci_iounmap() somewhat illogically comes from lib/iomap.c for the
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* CONFIG_GENERIC_IOMAP case, because that's the code that knows about
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* the different IOMAP ranges.
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*
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* But if the architecture does not use the generic iomap code, and if
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* it has _not_ defined it's own private pci_iounmap function, we define
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* it here.
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*
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* NOTE! This default implementation assumes that if the architecture
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* support ioport mapping (HAS_IOPORT_MAP), the ioport mapping will
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* be fixed to the range [ PCI_IOBASE, PCI_IOBASE+IO_SPACE_LIMIT [,
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* and does not need unmapping with 'ioport_unmap()'.
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*
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* If you have different rules for your architecture, you need to
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* implement your own pci_iounmap() that knows the rules for where
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* and how IO vs MEM get mapped.
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*
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* This code is odd, and the ARCH_HAS/ARCH_WANTS #define logic comes
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* from legacy <asm-generic/io.h> header file behavior. In particular,
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* it would seem to make sense to do the iounmap(p) for the non-IO-space
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* case here regardless, but that's not what the old header file code
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* did. Probably incorrectly, but this is meant to be bug-for-bug
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* compatible.
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*/
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#if defined(ARCH_WANTS_GENERIC_PCI_IOUNMAP)
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void pci_iounmap(struct pci_dev *dev, void __iomem *p)
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{
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#ifdef ARCH_HAS_GENERIC_IOPORT_MAP
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uintptr_t start = (uintptr_t) PCI_IOBASE;
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uintptr_t addr = (uintptr_t) p;
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if (addr >= start && addr < start + IO_SPACE_LIMIT)
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return;
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iounmap(p);
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#endif
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}
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EXPORT_SYMBOL(pci_iounmap);
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#endif /* ARCH_WANTS_GENERIC_PCI_IOUNMAP */
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#endif /* CONFIG_PCI */
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