402 lines
12 KiB
C
402 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 Sanechips Technology Co., Ltd.
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* Copyright 2017 Linaro Ltd.
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*
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* Author: Baoyou Xie <baoyou.xie@linaro.org>
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*/
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <sound/tlv.h>
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#define AUD96P22_RESET 0x00
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#define RST_DAC_DPZ BIT(0)
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#define RST_ADC_DPZ BIT(1)
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#define AUD96P22_I2S1_CONFIG_0 0x03
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#define I2S1_MS_MODE BIT(3)
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#define I2S1_MODE_MASK 0x7
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#define I2S1_MODE_RIGHT_J 0x0
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#define I2S1_MODE_I2S 0x1
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#define I2S1_MODE_LEFT_J 0x2
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#define AUD96P22_PD_0 0x15
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#define AUD96P22_PD_1 0x16
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#define AUD96P22_PD_3 0x18
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#define AUD96P22_PD_4 0x19
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#define AUD96P22_MUTE_0 0x1d
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#define AUD96P22_MUTE_2 0x1f
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#define AUD96P22_MUTE_4 0x21
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#define AUD96P22_RECVOL_0 0x24
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#define AUD96P22_RECVOL_1 0x25
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#define AUD96P22_PGA1VOL_0 0x26
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#define AUD96P22_PGA1VOL_1 0x27
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#define AUD96P22_LMVOL_0 0x34
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#define AUD96P22_LMVOL_1 0x35
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#define AUD96P22_HS1VOL_0 0x38
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#define AUD96P22_HS1VOL_1 0x39
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#define AUD96P22_PGA1SEL_0 0x47
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#define AUD96P22_PGA1SEL_1 0x48
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#define AUD96P22_LDR1SEL_0 0x59
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#define AUD96P22_LDR1SEL_1 0x60
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#define AUD96P22_LDR2SEL_0 0x5d
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#define AUD96P22_REG_MAX 0xfb
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struct aud96p22_priv {
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struct regmap *regmap;
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};
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static int aud96p22_adc_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
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struct regmap *regmap = priv->regmap;
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if (event != SND_SOC_DAPM_POST_PMU)
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return -EINVAL;
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/* Assert/de-assert the bit to reset ADC data path */
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regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, 0);
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regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, RST_ADC_DPZ);
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return 0;
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}
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static int aud96p22_dac_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
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struct regmap *regmap = priv->regmap;
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if (event != SND_SOC_DAPM_POST_PMU)
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return -EINVAL;
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/* Assert/de-assert the bit to reset DAC data path */
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regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, 0);
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regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, RST_DAC_DPZ);
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return 0;
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}
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static const DECLARE_TLV_DB_SCALE(lm_tlv, -11550, 50, 0);
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static const DECLARE_TLV_DB_SCALE(hs_tlv, -3900, 300, 0);
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static const DECLARE_TLV_DB_SCALE(rec_tlv, -9550, 50, 0);
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static const DECLARE_TLV_DB_SCALE(pga_tlv, -1800, 100, 0);
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static const struct snd_kcontrol_new aud96p22_snd_controls[] = {
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/* Volume control */
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SOC_DOUBLE_R_TLV("Master Playback Volume", AUD96P22_LMVOL_0,
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AUD96P22_LMVOL_1, 0, 0xff, 0, lm_tlv),
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SOC_DOUBLE_R_TLV("Headphone Volume", AUD96P22_HS1VOL_0,
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AUD96P22_HS1VOL_1, 0, 0xf, 0, hs_tlv),
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SOC_DOUBLE_R_TLV("Master Capture Volume", AUD96P22_RECVOL_0,
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AUD96P22_RECVOL_1, 0, 0xff, 0, rec_tlv),
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SOC_DOUBLE_R_TLV("Analogue Capture Volume", AUD96P22_PGA1VOL_0,
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AUD96P22_PGA1VOL_1, 0, 0x37, 0, pga_tlv),
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/* Mute control */
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SOC_DOUBLE("Master Playback Switch", AUD96P22_MUTE_2, 0, 1, 1, 1),
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SOC_DOUBLE("Headphone Switch", AUD96P22_MUTE_2, 4, 5, 1, 1),
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SOC_DOUBLE("Line Out Switch", AUD96P22_MUTE_4, 0, 1, 1, 1),
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SOC_DOUBLE("Speaker Switch", AUD96P22_MUTE_4, 2, 3, 1, 1),
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SOC_DOUBLE("Master Capture Switch", AUD96P22_MUTE_0, 0, 1, 1, 1),
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SOC_DOUBLE("Analogue Capture Switch", AUD96P22_MUTE_0, 2, 3, 1, 1),
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};
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/* Input mux kcontrols */
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static const unsigned int ain_mux_values[] = {
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0, 1, 3, 4, 5,
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};
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static const char * const ainl_mux_texts[] = {
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"AINL1 differential",
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"AINL1 single-ended",
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"AINL3 single-ended",
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"AINL2 differential",
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"AINL2 single-ended",
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};
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static const char * const ainr_mux_texts[] = {
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"AINR1 differential",
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"AINR1 single-ended",
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"AINR3 single-ended",
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"AINR2 differential",
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"AINR2 single-ended",
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};
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static SOC_VALUE_ENUM_SINGLE_DECL(ainl_mux_enum, AUD96P22_PGA1SEL_0,
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0, 0x7, ainl_mux_texts, ain_mux_values);
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static SOC_VALUE_ENUM_SINGLE_DECL(ainr_mux_enum, AUD96P22_PGA1SEL_1,
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0, 0x7, ainr_mux_texts, ain_mux_values);
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static const struct snd_kcontrol_new ainl_mux_kcontrol =
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SOC_DAPM_ENUM("AINL Mux", ainl_mux_enum);
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static const struct snd_kcontrol_new ainr_mux_kcontrol =
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SOC_DAPM_ENUM("AINR Mux", ainr_mux_enum);
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/* Output mixer kcontrols */
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static const struct snd_kcontrol_new ld1_left_kcontrols[] = {
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SOC_DAPM_SINGLE("DACL LD1L Switch", AUD96P22_LDR1SEL_0, 0, 1, 0),
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SOC_DAPM_SINGLE("AINL LD1L Switch", AUD96P22_LDR1SEL_0, 1, 1, 0),
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SOC_DAPM_SINGLE("AINR LD1L Switch", AUD96P22_LDR1SEL_0, 2, 1, 0),
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};
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static const struct snd_kcontrol_new ld1_right_kcontrols[] = {
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SOC_DAPM_SINGLE("DACR LD1R Switch", AUD96P22_LDR1SEL_1, 8, 1, 0),
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SOC_DAPM_SINGLE("AINR LD1R Switch", AUD96P22_LDR1SEL_1, 9, 1, 0),
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SOC_DAPM_SINGLE("AINL LD1R Switch", AUD96P22_LDR1SEL_1, 10, 1, 0),
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};
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static const struct snd_kcontrol_new ld2_kcontrols[] = {
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SOC_DAPM_SINGLE("DACL LD2 Switch", AUD96P22_LDR2SEL_0, 0, 1, 0),
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SOC_DAPM_SINGLE("AINL LD2 Switch", AUD96P22_LDR2SEL_0, 1, 1, 0),
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SOC_DAPM_SINGLE("DACR LD2 Switch", AUD96P22_LDR2SEL_0, 2, 1, 0),
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};
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static const struct snd_soc_dapm_widget aud96p22_dapm_widgets[] = {
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/* Overall power bit */
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SND_SOC_DAPM_SUPPLY("POWER", AUD96P22_PD_0, 0, 0, NULL, 0),
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/* Input pins */
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SND_SOC_DAPM_INPUT("AINL1P"),
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SND_SOC_DAPM_INPUT("AINL2P"),
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SND_SOC_DAPM_INPUT("AINL3"),
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SND_SOC_DAPM_INPUT("AINL1N"),
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SND_SOC_DAPM_INPUT("AINL2N"),
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SND_SOC_DAPM_INPUT("AINR2N"),
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SND_SOC_DAPM_INPUT("AINR1N"),
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SND_SOC_DAPM_INPUT("AINR3"),
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SND_SOC_DAPM_INPUT("AINR2P"),
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SND_SOC_DAPM_INPUT("AINR1P"),
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/* Input muxes */
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SND_SOC_DAPM_MUX("AINLMUX", AUD96P22_PD_1, 2, 0, &ainl_mux_kcontrol),
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SND_SOC_DAPM_MUX("AINRMUX", AUD96P22_PD_1, 3, 0, &ainr_mux_kcontrol),
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/* ADCs */
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SND_SOC_DAPM_ADC_E("ADCL", "Capture Left", AUD96P22_PD_1, 0, 0,
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aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
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SND_SOC_DAPM_ADC_E("ADCR", "Capture Right", AUD96P22_PD_1, 1, 0,
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aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
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/* DACs */
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SND_SOC_DAPM_DAC_E("DACL", "Playback Left", AUD96P22_PD_3, 0, 0,
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aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
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SND_SOC_DAPM_DAC_E("DACR", "Playback Right", AUD96P22_PD_3, 1, 0,
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aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
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/* Output mixers */
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SND_SOC_DAPM_MIXER("LD1L", AUD96P22_PD_3, 6, 0, ld1_left_kcontrols,
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ARRAY_SIZE(ld1_left_kcontrols)),
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SND_SOC_DAPM_MIXER("LD1R", AUD96P22_PD_3, 7, 0, ld1_right_kcontrols,
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ARRAY_SIZE(ld1_right_kcontrols)),
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SND_SOC_DAPM_MIXER("LD2", AUD96P22_PD_4, 2, 0, ld2_kcontrols,
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ARRAY_SIZE(ld2_kcontrols)),
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/* Headset power switch */
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SND_SOC_DAPM_SUPPLY("HS1L", AUD96P22_PD_3, 4, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("HS1R", AUD96P22_PD_3, 5, 0, NULL, 0),
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/* Output pins */
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SND_SOC_DAPM_OUTPUT("HSOUTL"),
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SND_SOC_DAPM_OUTPUT("LINEOUTL"),
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SND_SOC_DAPM_OUTPUT("LINEOUTMP"),
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SND_SOC_DAPM_OUTPUT("LINEOUTMN"),
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SND_SOC_DAPM_OUTPUT("LINEOUTR"),
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SND_SOC_DAPM_OUTPUT("HSOUTR"),
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};
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static const struct snd_soc_dapm_route aud96p22_dapm_routes[] = {
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{ "AINLMUX", "AINL1 differential", "AINL1N" },
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{ "AINLMUX", "AINL1 single-ended", "AINL1P" },
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{ "AINLMUX", "AINL3 single-ended", "AINL3" },
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{ "AINLMUX", "AINL2 differential", "AINL2N" },
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{ "AINLMUX", "AINL2 single-ended", "AINL2P" },
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{ "AINRMUX", "AINR1 differential", "AINR1N" },
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{ "AINRMUX", "AINR1 single-ended", "AINR1P" },
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{ "AINRMUX", "AINR3 single-ended", "AINR3" },
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{ "AINRMUX", "AINR2 differential", "AINR2N" },
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{ "AINRMUX", "AINR2 single-ended", "AINR2P" },
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{ "ADCL", NULL, "AINLMUX" },
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{ "ADCR", NULL, "AINRMUX" },
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{ "ADCL", NULL, "POWER" },
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{ "ADCR", NULL, "POWER" },
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{ "DACL", NULL, "POWER" },
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{ "DACR", NULL, "POWER" },
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{ "LD1L", "DACL LD1L Switch", "DACL" },
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{ "LD1L", "AINL LD1L Switch", "AINLMUX" },
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{ "LD1L", "AINR LD1L Switch", "AINRMUX" },
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{ "LD1R", "DACR LD1R Switch", "DACR" },
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{ "LD1R", "AINR LD1R Switch", "AINRMUX" },
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{ "LD1R", "AINL LD1R Switch", "AINLMUX" },
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{ "LD2", "DACL LD2 Switch", "DACL" },
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{ "LD2", "AINL LD2 Switch", "AINLMUX" },
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{ "LD2", "DACR LD2 Switch", "DACR" },
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{ "HSOUTL", NULL, "LD1L" },
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{ "HSOUTR", NULL, "LD1R" },
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{ "HSOUTL", NULL, "HS1L" },
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{ "HSOUTR", NULL, "HS1R" },
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{ "LINEOUTL", NULL, "LD1L" },
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{ "LINEOUTR", NULL, "LD1R" },
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{ "LINEOUTMP", NULL, "LD2" },
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{ "LINEOUTMN", NULL, "LD2" },
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};
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static const struct snd_soc_component_driver aud96p22_driver = {
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.controls = aud96p22_snd_controls,
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.num_controls = ARRAY_SIZE(aud96p22_snd_controls),
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.dapm_widgets = aud96p22_dapm_widgets,
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.num_dapm_widgets = ARRAY_SIZE(aud96p22_dapm_widgets),
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.dapm_routes = aud96p22_dapm_routes,
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.num_dapm_routes = ARRAY_SIZE(aud96p22_dapm_routes),
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.idle_bias_on = 1,
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.use_pmdown_time = 1,
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.endianness = 1,
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.non_legacy_dai_naming = 1,
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};
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static int aud96p22_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct aud96p22_priv *priv = snd_soc_component_get_drvdata(dai->component);
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struct regmap *regmap = priv->regmap;
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unsigned int val;
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/* Master/slave mode */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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val = 0;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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val = I2S1_MS_MODE;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MS_MODE, val);
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/* Audio format */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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val = I2S1_MODE_RIGHT_J;
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break;
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case SND_SOC_DAIFMT_I2S:
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val = I2S1_MODE_I2S;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val = I2S1_MODE_LEFT_J;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MODE_MASK, val);
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return 0;
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}
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static const struct snd_soc_dai_ops aud96p22_dai_ops = {
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.set_fmt = aud96p22_set_fmt,
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};
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#define AUD96P22_RATES SNDRV_PCM_RATE_8000_192000
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#define AUD96P22_FORMATS (\
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SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
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static struct snd_soc_dai_driver aud96p22_dai = {
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.name = "aud96p22-dai",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = AUD96P22_RATES,
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.formats = AUD96P22_FORMATS,
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},
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.capture = {
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.stream_name = "Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = AUD96P22_RATES,
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.formats = AUD96P22_FORMATS,
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},
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.ops = &aud96p22_dai_ops,
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};
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static const struct regmap_config aud96p22_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = AUD96P22_REG_MAX,
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.cache_type = REGCACHE_RBTREE,
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};
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static int aud96p22_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct device *dev = &i2c->dev;
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struct aud96p22_priv *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (priv == NULL)
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return -ENOMEM;
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priv->regmap = devm_regmap_init_i2c(i2c, &aud96p22_regmap);
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if (IS_ERR(priv->regmap)) {
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ret = PTR_ERR(priv->regmap);
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dev_err(dev, "failed to init i2c regmap: %d\n", ret);
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return ret;
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}
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i2c_set_clientdata(i2c, priv);
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ret = devm_snd_soc_register_component(dev, &aud96p22_driver, &aud96p22_dai, 1);
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if (ret) {
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dev_err(dev, "failed to register component: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int aud96p22_i2c_remove(struct i2c_client *i2c)
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{
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return 0;
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}
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static const struct of_device_id aud96p22_dt_ids[] = {
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{ .compatible = "zte,zx-aud96p22", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, aud96p22_dt_ids);
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static struct i2c_driver aud96p22_i2c_driver = {
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.driver = {
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.name = "zx_aud96p22",
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.of_match_table = aud96p22_dt_ids,
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},
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.probe = aud96p22_i2c_probe,
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.remove = aud96p22_i2c_remove,
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};
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module_i2c_driver(aud96p22_i2c_driver);
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MODULE_DESCRIPTION("ZTE ASoC AUD96P22 CODEC driver");
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MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
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MODULE_LICENSE("GPL v2");
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