248 lines
6.9 KiB
C
248 lines
6.9 KiB
C
/*
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/gic.h>
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#include <asm/localtimer.h>
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#include <asm/sched_clock.h>
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#include <mach/msm_iomap.h>
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#include <mach/cpu.h>
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#include <mach/board.h>
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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#define TIMER_ENABLE 0x0008
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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#define DGT_CLK_CTL 0x0034
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#define DGT_CLK_CTL_DIV_4 0x3
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#define GPT_HZ 32768
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#define MSM_DGT_SHIFT 5
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static void __iomem *event_base;
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
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/* Stop the timer tick */
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if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
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u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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ctrl &= ~TIMER_ENABLE_EN;
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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}
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int msm_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
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writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
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return 0;
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}
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static void msm_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 ctrl;
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ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
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switch (mode) {
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Timer is enabled in set_next_event */
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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break;
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}
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writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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}
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static struct clock_event_device msm_clockevent = {
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.name = "gp_timer",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = msm_timer_set_next_event,
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.set_mode = msm_timer_set_mode,
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};
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static union {
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struct clock_event_device *evt;
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struct clock_event_device __percpu **percpu_evt;
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} msm_evt;
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static void __iomem *source_base;
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static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
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{
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return readl_relaxed(source_base + TIMER_COUNT_VAL);
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}
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static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
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{
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/*
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* Shift timer count down by a constant due to unreliable lower bits
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* on some targets.
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*/
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return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
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}
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static struct clocksource msm_clocksource = {
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.name = "dg_timer",
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.rating = 300,
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.read = msm_read_timer_count,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#ifdef CONFIG_LOCAL_TIMERS
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static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
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{
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/* Use existing clock_event for cpu 0 */
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if (!smp_processor_id())
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return 0;
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writel_relaxed(0, event_base + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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evt->irq = msm_clockevent.irq;
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evt->name = "local_timer";
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evt->features = msm_clockevent.features;
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evt->rating = msm_clockevent.rating;
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evt->set_mode = msm_timer_set_mode;
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evt->set_next_event = msm_timer_set_next_event;
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evt->shift = msm_clockevent.shift;
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evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
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evt->min_delta_ns = clockevent_delta2ns(4, evt);
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*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
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clockevents_register_device(evt);
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enable_percpu_irq(evt->irq, 0);
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return 0;
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}
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static void msm_local_timer_stop(struct clock_event_device *evt)
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{
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evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
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disable_percpu_irq(evt->irq);
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}
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static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
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.setup = msm_local_timer_setup,
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.stop = msm_local_timer_stop,
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};
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#endif /* CONFIG_LOCAL_TIMERS */
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static notrace u32 msm_sched_clock_read(void)
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{
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return msm_clocksource.read(&msm_clocksource);
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}
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static void __init msm_timer_init(void)
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{
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struct clock_event_device *ce = &msm_clockevent;
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struct clocksource *cs = &msm_clocksource;
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int res;
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u32 dgt_hz;
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if (cpu_is_msm7x01()) {
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event_base = MSM_CSR_BASE;
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source_base = MSM_CSR_BASE + 0x10;
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dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
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cs->read = msm_read_timer_count_shift;
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cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
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} else if (cpu_is_msm7x30()) {
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event_base = MSM_CSR_BASE + 0x04;
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source_base = MSM_CSR_BASE + 0x24;
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dgt_hz = 24576000 / 4;
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} else if (cpu_is_qsd8x50()) {
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event_base = MSM_CSR_BASE;
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source_base = MSM_CSR_BASE + 0x10;
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dgt_hz = 19200000 / 4;
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} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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event_base = MSM_TMR_BASE + 0x04;
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/* Use CPU0's timer as the global clock source. */
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source_base = MSM_TMR0_BASE + 0x24;
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dgt_hz = 27000000 / 4;
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writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
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} else
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BUG();
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writel_relaxed(0, event_base + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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ce->cpumask = cpumask_of(0);
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ce->irq = INT_GP_TIMER_EXP;
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clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
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if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
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if (!msm_evt.percpu_evt) {
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pr_err("memory allocation failed for %s\n", ce->name);
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goto err;
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}
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*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
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res = request_percpu_irq(ce->irq, msm_timer_interrupt,
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ce->name, msm_evt.percpu_evt);
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if (!res) {
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enable_percpu_irq(ce->irq, 0);
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#ifdef CONFIG_LOCAL_TIMERS
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local_timer_register(&msm_local_timer_ops);
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#endif
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}
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} else {
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msm_evt.evt = ce;
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res = request_irq(ce->irq, msm_timer_interrupt,
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IRQF_TIMER | IRQF_NOBALANCING |
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IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
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}
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if (res)
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pr_err("request_irq failed for %s\n", ce->name);
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err:
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writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
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res = clocksource_register_hz(cs, dgt_hz);
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if (res)
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pr_err("clocksource_register failed\n");
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setup_sched_clock(msm_sched_clock_read,
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cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
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}
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struct sys_timer msm_timer = {
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.init = msm_timer_init
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};
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